Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, Species CC in the reply filed on 11/20/25 is acknowledged.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected product/species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/20/25.
Priority
The instant application contains additional disclosure not presented in the previous applications in the family and therefore the claims have different priority dates based on when the subject matter was disclosed. It is noted that figures 26B-86 were not included in application 16/849600 and figures 41-86 were not included in application 17/090420, and Figures 63-86 were not included in application 17/543987, figures 69-86 are not included in application 18/145275 and figures 80-86 are not included in application 18/154286 .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-8 and 13 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 8-10 of copending Application No. 18/154286 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because they contain the same subject matter.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Eom et al. (US PGPub 2020/0388686) in view of Choi et al. (US PGPub 2021/0388686).
Claim 1: Eom teaches a method of forming a memory device, comprising: forming an alternating stack of disposable material layers (13) and silicon nitride layers (12) over a substrate (Fig. 10A); forming a memory opening (14) through the alternating stack (Fig. 10B); forming a memory film (15, 16) in the memory opening; forming a vertical semiconductor channel (17) over the memory film in the memory opening ((Fig. 10C); forming a backside trench (21) through the alternating stack (Fig. 10D); forming laterally-extending cavities (22) by removing the disposable material layers selective to the silicon nitride layers through the backside trench (Fig. 10E); and replacing remaining portions of the silicon nitride layers with electrically conductive layer (28A) (Fig. 10H-10I). Eom does not teach oxidizing portions of the silicon nitride layers exposed in the laterally-extending cavities to form insulating layers. Choi teaches oxidizing portions of the remaining alternating insulating layer (Fig. 12K) [0134] to prevent cell interference due to charge diffusion between cells [0004].Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the method taught by Eom to have included oxidizing the SiN layer and creating a discrete charge storage pattern to improve device performance as taught by Choi [0004].
Claim 2: Choi teaches (Fig. 12D) forming an in-process dielectric liner layer in the memory opening prior to the forming the memory film in the memory opening.
Claim 3: Choi teaches (Fig. 12D-E) thinning the in-process dielectric liner layer to form a dielectric liner layer having a lesser thickness than the in-process dielectric liner layer.
Claim 4: Choi teaches [0130] wherein the dielectric liner layer comprises a silicon nitride dielectric liner layer.
Claim 5: Choi teaches (Fig. 12J-K) oxidizing annular portions of the silicon nitride dielectric liner layer exposed in the laterally-extending cavities at a same time as oxidizing portions of the silicon nitride layers to form the insulating layers.
Claim 6: Choi teaches (Fig. 12J-K) the oxidizing converts the annular portions of the silicon nitride dielectric liner layer into vertical portions of the insulating layers; and the oxidizing converts portions of the silicon nitride layers exposed in the laterally-extending cavities into the horizontal portions of the insulating layers.
Claim 8: Choi teaches (Fig. 4B, 7, 9) wherein an air gap (AG1/2/3) is formed in each of the insulating layers during the oxidizing.
Claim 9: Choi teaches (Fig. 12I) the laterally-extending cavities are formed by removing the disposable material layers selective to the silicon nitride layers and selective to the silicon nitride dielectric liner layer to leave the annular portions of the silicon nitride dielectric liner layer exposed in the laterally-extending cavities.
Claim 10: Choi teaches (Fig. 12D-E) the silicon nitride layers comprise cylindrical sidewalls that are exposed to the memory opening after formation of the memory opening; a local cavity within one of the silicon nitride layers is formed during formation of the memory opening, the local cavity laterally extending outward from a cylindrical vertical plane including the cylindrical sidewalls; and a silicon nitride fill material portion of the in-process dielectric liner layer fills the local cavity.
Claim 11: Choi teaches (Fig. 12C) comprising laterally recessing the silicon nitride layers in the memory opening relative to the disposable material layers.
Claim 12: Choi teaches (Fig. 12J-K) the step of replacing the remaining portions of the silicon nitride layers with the electrically conductive layers comprises: removing the remaining portions of the silicon nitride layers and remaining portions of the silicon nitride dielectric liner layer through the backside trench selective to the insulating layers and to the memory film to form backside recesses; and forming the electrically conductive layers in the backside recesses through the backside trench.
Claim 14: Choi teaches [0045] the insulating layers comprise silicon oxide insulating layers.
Allowable Subject Matter
Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814
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