DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: “151,” as shown in Fig. 1, for example. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 3, 7 – 10, 12 – 16, and 18 – 20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US Patent No. 11,211,350 to Hsu et al.
Regarding claims 1 and 9, Hsu et al. teach an electronic device (see marked up portion of Fig. 1F below), comprising:
a multilevel package substrate having first and second levels in respective first and second planes of orthogonal first and second directions in a stack along a third direction Z that is orthogonal to the first and second directions, the first level including a first conductive feature, and the second level including a second conductive feature (Marked up fig. below); and
a semiconductor die (120) having a conductive peripheral terminal (see mark up of fig. 1F), a conductive interior terminal (Adjacent peripheral terminal), a peripheral region, and an interior region;
wherein the interior region is inwardly spaced from lateral sides of the semiconductor die, the peripheral region laterally surrounds the interior region and extends laterally between the interior region and the lateral sides of the semiconductor die, the conductive peripheral terminal (a single peripheral terminal on one side of the peripheral region meets the limitation) extends along the third direction from the peripheral region to the first level of the
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multilevel package substrate, the conductive interior terminal is laterally spaced apart from the peripheral terminal and extends along the third direction from the interior region to the first level of the multilevel package substrate, the peripheral terminal is coupled to a peripheral contact portion (See mark up above)) of the first conductive feature, and the second level of the multilevel package substrate has no conductive feature under the peripheral contact portion of the first conductive feature (See circled region in marked up fig. 1F).
Regarding claim 2, Hsu et al. teach an electronic device, comprising a package structure that encloses the semiconductor die and a portion of the multilevel package substrate (Fig. 1F).
Regarding claims 3 and 10, Hsu et al. teach an elecronic device, wherein the multilevel package substrate comprises more than two levels, including a third level in a third plane of the first and second directions, the second level between the first and third levels along the third direction, and the third level including a third conductive feature. See marked up Fig. 1F, where a third level and third conductive feature is disposed beneath the second level.
Regardign claims 7 and 14, Hsu et al. teach an electronic device, wherein the first and second conductive features of the respective first and second levels include copper (Col. 4, lines 11 – 19).
Regarding claim 8, Hsu et al. teach an electronic device, wherein the multilevel package substrate has dielectric material extending between the conductive feature within and between the respective first and second levels (Col. 3, line 66 to Col. 4, line 10).
Regarding claim 13, Hsu et al. teach a multilevel package, wherein the second level of the multilevel package substrate has a second instance of the second conductive features that is at least partially under the interior contact portion of the second instance of the first conductive features of the first level.
Regarding claim 15, Hsu et al. teach a method of fabricating an electronic device, the method (See marked up Fig. 1F above) comprising:
forming a multilevel package substrate, including:
forming a first level having first conductive features and extending in a first plane of orthogonal first and second directions in peripheral and interior regions, wherein a first instance of the first conductive features has a peripheral contact portion in the peripheral region; and
forming a second level having second conductive features in a second plane of the first and second directions in the peripheral and interior regions, the second level arranged with the first level in a stack along a third direction Z that is orthogonal to the first and second directions, wherein the second level has no conductive feature under the peripheral contact portion of the first instance of the first conductive features;
attaching a semiconductor die (120) to the multilevel package substrate;
electrically coupling a conductive peripheral terminal (a single peripheral terminal on one side of the peripheral region meets the limitation) of the semiconductor die to the peripheral contact portion of the first instance of the first conductive features; and
forming a package structure that encloses the semiconductor die and a portion of the multilevel package substrate. See Fig. 1F.
Regarding claim 16, Hsu et al. teach a method, wherein forming the multilevel package substrate further includes forming a third level in the stack with the second level between the first and third levels along the third direction, and the third level including third conductive features. See marked up Fig. 1F above.
Regarding claim 18, Hsu et al. teach a method, wherein a second instance of the first conductive features has an interior contact portion in the interior region;
the method further comprising electrically coupling a conductive interior terminal of the semiconductor die to the interior contact portion of the second instance of the first conductive features of the first level. See marked up Fig. 1F above.
Regarding claim 19, Hsu et al. teach a method, wherein the second level of the multilevel package substrate has a second instance of the second conductive features that is at least partially under the interior contact portion of the second instance of the first conductive features of the first level. See marked up Fig. 1F above.
Regarding claim 20, Hsu et al. teach a method, wherein forming the multilevel package substrate further includes forming dielectric material extending between the conductive feature within and between the respective first and second levels (Col. 3, line 66 to Col. 4, line 10).
Allowable Subject Matter
Claims 4 – 6, 11, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication No. 2024/0203893 to Tsai et al. teach an electronic device comprising a multilevel package substrate having first and second levels including a die and peripheral region and interior region. Tsai et al. do not teach that the peripheral terminal is coupled to a peripheral contact portion of the first conductive feature, and the second level of the multilevel package substrate has no conductive feature under the peripheral contact portion of the first conductive feature.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS W OWENS whose telephone number is (571)272-1662. The examiner can normally be reached M-F 5:30-1:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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DOUGLAS W. OWENS, Esq.
Primary Patent Examiner
Art Unit 2897
/DOUGLAS W OWENS/Primary Patent Examiner, Art Unit 2897