DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 06/30/2023, is/are in compliance with the provisions 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-5, 7, 11-14 and 18-20 is/are rejected under 35 U.S.C. 102 as being anticipated by Murayama et al. (US 8394678) herein referred to as Murayama.
As to claim(s) 1, Murayama discloses a semiconductor package comprising:
a package substrate (Fig. 7, package substrate (65) Murayama), wherein a plurality of bonding pads (Fig. 7, connection terminals (67) + (pad item 14 (fig 1 related art) Murayama) are arranged on an upper surface of the package substrate (Fig. 7, (65) Murayama);
a semiconductor chip (Fig. 7, semiconductor chip stacked chip (60)/(21) of fig 2 embodiment, Murayama) mounted on the upper surface of the package substrate (Fig. 7, (65) Murayama), wherein
a plurality of chip pads ([col 30, lines 38-42] “each of the chip sealing body including a semiconductor chip having a semiconductor integrated circuit, a pad and a conductive connecting material, and a resin sealing the semiconductor chip, “ Murayama) are arranged on an upper surface of the semiconductor chip (Fig. 7, semiconductor chip stacked chip (60) )/(21) of fig 2 embodiment Murayama);
a first adhesive film (Fig. 7, 1st adhesive (66) Murayama) attached to a lower surface of the semiconductor chip (Fig. 7, semiconductor chip stacked chip (60) Murayama)) wherein
the first adhesive film (Fig. 7, (66) Murayama) has a first area corresponding to an area of the semiconductor chip (Fig. 7, semiconductor chip stacked chip (60) )/(21) of fig 2 embodiment Murayama);
a second adhesive film (Fig. 7, 2nd adhesive (61) Murayama) attached to the upper surface of the package substrate (Fig. 7, package substrate (65) Murayama), wherein
the second adhesive film (Fig. 7, (61) Murayama) is in direct contact with the first adhesive film (Fig. 7, (66) Murayama), and
the second adhesive film (Fig. 7, (61) Murayama) has a second area larger than the first area; ([col 23 lines 14-17 “The back surface side of the semiconductor chips located on the opposite side to the integrated circuit surface is sealed by the DAF having a function of the sealing resin.” See Fig. 7 (61) and (66). Thus, Fig. 7 shows the DAF (61) adhesive film on both sides of the chip, larger in area than the first area (66).)
a plurality of bonding wires (Fig. 7, (64) Murayama) respectively connecting the plurality of bonding pads (67+ 14, Murayama) ([col 8 line 5-7] “bonding wire (64) is connected to connection terminals (67) of the wiring substrate (65) respectively, Murayama );
to the plurality of chip pads (Annotated chip pads, Murayama; See Fig. 2 embodiment for chip number (22) “A conductive connecting material 23 is connected to pads 22 of a semiconductor chip 21 respectively, and the whole surface of the semiconductor chip 21”); and
a molding structure (“[col 8 lines 7-10] The chip stacked body, the connection terminals on the wiring substrate, and the wiring substrate are sealed with an insulating resin (68), whereby the semiconductor chip stacked body 60 is formed”, Murayama) disposed on the upper surface of the package substrate, the molding portion covering the semiconductor chip (Fig 7 (60)/(21) of fig 2 embodiment, Murayama) and the plurality of bonding wires (bonding wire (64) Fig.7 Murayama).
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As to claim(s) 3, Murayama discloses the semiconductor package of claim 1, and further discloses wherein
the second adhesive film (2nd adhesive Fig. 7 (61) Murayama) has portions respectively extending from edges (Fig. 7 shows (61) extending from edges of chip on the upper surface of the substrate, Murayama) of the semiconductor chip ((Fig 7 (60)/(21) of fig 2 embodiment, Murayama)); on the upper surface of the package substrate (65) Murayama).
As to claim(s) 4, Murayama discloses the semiconductor package of claim 3, and further discloses wherein
the edges include a first pair of edges (1st pair edges of the chip (Fig. 7 (60), Fig. 26B (251), Murayama) opposing each other in a first direction and
a second pair of edges (2nd pair edges of the chip (Fig. 7 (60), Fig. 26B (251), Murayama) opposing each other in a second direction, wherein
portions (2nd adhesive portions, Fig. 7 (61) Murayama) extending from the first pair of edges have a first width, and wherein
the second pair of edges (2nd pair edges of the chip (Fig. 7 (60), Fig. 26B (251), Murayama) have a second width wider than the first width.
As to claim(s) 5, Murayama discloses the semiconductor package of claim 4, and further discloses wherein
the plurality of bonding pads (Fig. 7, connection terminals (67 + (14 of Fig. 2)), Murayama) are arranged in a pair of regions respectively adjacent to the first pair of edges (1st pair edges of the chip Fig. 7 (60)/(14) of Fig. 2 embodiment, Murayama) of the semiconductor chip, and
are not arranged in a pair of regions respectively adjacent to the second pair of edges (2nd pair edges of the chip Fig. 7 (60)/(14) of Fig. 2 embodiment, Murayama).
As to claim(s) 7, Murayama discloses the semiconductor package of claim 1, and further discloses wherein
a thickness of the second adhesive film (Fig. 7, 2nd adhesive (61) Murayama) is in a range of 10 μm to 100 μm [col 12 lines 66-67 and col 13 lines 1-3] “Respective chip sealing bodies are adhered/fixed mutually in the thickness direction by using a die attach film 124 whose thickness is 10 .mu.m to 100 .mu.m.”).
As to claim(s) 11, Murayama discloses semiconductor package of claim 1, further comprising:
at least a second semiconductor chip stacked on the upper surface of the semiconductor chip (Fig. 7, semiconductor chip stacked chip (60)/(14) of Fig. 2 embodiment, Murayama).
As to claim(s) 12, Murayama discloses a semiconductor package further comprising:
a package substrate, (Fig. 7, package substrate (65) Murayama), wherein a plurality of bonding pads (Fig. 7, connection terminals (67) + (pad item 14 (fig 1 related art) Murayama) are arranged on an upper surface of the package substrate (Fig. 7, (65) Murayama);
a first semiconductor chip (Annotated chip Fig. 7 (60)/(14) of Fig. 2 embodiment, Murayama) mounted on the upper surface of the package substrate (Fig. 7, (65) Murayama)
a plurality of first chip pads ([col 30, lines 38-42] “each of the chip sealing body including a semiconductor chip having a semiconductor integrated circuit, a pad and a conductive connecting material, and a resin sealing the semiconductor chip, “ Murayama) are arranged on an upper surface of the first semiconductor chip (Fig. 7, semiconductor chip stacked chip (60) )/(21) of fig 2 embodiment Murayama);
a second semiconductor chip (Annotated Fig. 7, semiconductor chip stacked chip (60)/(14) of Fig. 2 embodiment, Murayama) mounted on the upper surface of the package substrate ((65) Murayama), wherein,
a first adhesive structure (Fig. 7, (66) Murayama) disposed between the package substrate (Fig. 7, package substrate (65) Murayama)and the first semiconductor chip (Annotated 1st chip Fig. 7 (60)/(14) of Fig. 2 embodiment, Murayama);
a second adhesive structure (Fig. 7, 2nd adhesive (61) Murayama) disposed between the package substrate (Fig. 7, package substrate (65) Murayama) and the second semiconductor chip (Annotated 2nd chip Fig. 7 (60)/(14) of Fig. 2 embodiment, Murayama);
a plurality of bonding wires (Fig. 7, (64) Murayama) respectively connecting the plurality of bonding pads (67+ 14, Murayama) ([col 8 line 5-7] “bonding wire (64) is connected to connection terminals (67) of the wiring substrate (65) respectively, Murayama ) and the plurality of first and second chip pads; and
a molding portion (“[col 8 lines 7-10] The chip stacked body, the connection terminals on the wiring substrate, and the wiring substrate are sealed with an insulating resin (68), whereby the semiconductor chip stacked body 60 is formed”, Murayama) disposed on the upper surface of the package substrate,
the molding portion (68) covering the first and second semiconductor chips and the plurality of bonding wires (See Fig.7 (68) covers stacked body, Murayama), wherein
the first adhesive structure includes a first adhesive film (Fig. 7, (66) Murayama) attached to a lower surface of the first semiconductor chip (Fig. 7, semiconductor chip stacked chip (60)/(21) of fig 2 embodiment, Murayama) and a lower surface of the second semiconductor chips (Annotated Fig. 7 2nd semiconductor chip), and wherein
the second adhesive structure includes a second adhesive film (Fig. 7, 2nd adhesive (61) Murayama) in direct contact with the first adhesive film (Fig. 7, (66) Murayama) and attached to the upper surface of the package substrate (Fig. 7, package substrate (65) Murayama), and wherein,
an area of the first adhesive film is larger than an area of the second adhesive film.
As to claim(s) 13, Murayama discloses the semiconductor package of claim 12, and further discloses wherein
the first adhesive film (Fig. 7 (61) Murayama),has areas corresponding to areas on the lower surface of the first semiconductor chip (Annotated 1st chip Fig. 7 (60)/(14) of Fig. 2 embodiment, Murayama) and the lower surface of the second semiconductor chip (Annotated chip Fig. 7 (60)/(14) of Fig. 2 embodiment, Murayama), and
the second adhesive film (Fig. 7 (66) Murayama) has portions respectively extending from edges of the first adhesive film (Fig. 7 (61) Murayama),on the upper surface of the package substrate.
As to claim(s) 14 and 19, Murayama discloses the semiconductor package of claim 13 and 18 respectively, further discloses wherein
the edges include a first pair of edges (1st pair of edges Fig. 7) opposing each other in a first direction and a second pair of edges (2nd pair of edges Fig. 7) opposing each other in a second direction, wherein
portions extending from the first pair of edges (1st pair of edges Fig. 7) have a first width, and wherein
portions extending from the second pair of edges (2nd pair of edges Fig. 7) have a second width wider than the first width.
As to claim(s) 18, Murayama discloses a semiconductor package comprising:
a package substrate ((Fig. 7, package substrate (65) Murayama), wherein a plurality of bonding pads (Fig. 7, connection terminals (67) + (pad item 14 (fig 1 related art) Murayama) are arranged on an upper surface of the package substrate (Fig. 7, (65) Murayama);
a semiconductor chip Annotated chip Fig. 7 (60)/(14) of Fig. 2 embodiment, Murayama) mounted on the upper surface of the package substrate (Fig. 7, (65) Murayama) wherein
a plurality of chip pads ([col 30, lines 38-42] “each of the chip sealing body including a semiconductor chip having a semiconductor integrated circuit, a pad and a conductive connecting material, and a resin sealing the semiconductor chip, “ Murayama) are arranged on an upper surface of the semiconductor chip (Fig. 7, semiconductor chip stacked chip (60) )/(21) of fig 2 embodiment Murayama);
a first adhesive film (Fig. 7, (66) Murayama) attached to a lower surface of the semiconductor chip ((Annotated chip Fig. 7 (60)/(14) of Fig. 2 embodiment, Murayama)), the first adhesive film having an area, corresponding to an area of the semiconductor chip;
a second adhesive film (Fig. 7, 2nd adhesive (61) Murayama) attached to the upper surface of the package substrate, wherein
the second adhesive film (Fig. 7, 2nd adhesive (61) Murayama) is disposed on and in direct contact with the first adhesive film (Fig. 7, (66) Murayama),
the second adhesive film having portions respectively extending from edges of the first adhesive film on the upper surface of the package substrate (Fig. 7 shows (61) extending from edges of chip on the upper surface of the substrate, Murayama);
a plurality of bonding wires (Fig. 7, (64) Murayama) respectively connecting the plurality of bonding pads (67+ 14, Murayama) ([col 8 line 5-7] “bonding wire (64) is connected to connection terminals (67) of the wiring substrate (65) respectively, Murayama) and the plurality of chip pads (Annotated chip pads Fig. 7 Murayama); and
a molding portion (“[col 8 lines 7-10] The chip stacked body, the connection terminals on the wiring substrate, and the wiring substrate are sealed with an insulating resin (68), whereby the semiconductor chip stacked body 60 is formed”, Murayama) disposed on the upper surface of the package substrate,
the molding portion covering the semiconductor chip (Fig 7 (60)/(14) of fig 2 embodiment, Murayama) and the plurality of bonding wires (bonding wire (64) Fig.7 Murayama).
As to claim(s) 20, Murayama discloses the semiconductor package of claim 19, wherein
the edges include a first pair of edges (1st pair of edges Fig. 7) opposing each other in a first direction and
a second pair of edges (2nd pair of edges Fig. 7) opposing each other in a second direction, wherein
the plurality of bonding pads (67+ 14, Murayama) ([col 8 line 5-7] “bonding wire (64) is connected to connection terminals (67) of the wiring substrate (65) respectively, Murayama ) are arranged in a pair of regions respectively adjacent to the first pair of edges (1st pair edges of the chip Fig. 7) of the semiconductor chip, and
are not arranged in a pair of regions respectively adjacent to the second pair of edges (2nd pair edges of the chip Fig. 7).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claim(s) 2, 8-9 and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Murayama et al. (US 8394678) herein referred to as Murayama
As to claim(s) 2, Murayama discloses the semiconductor package of claim 1 as discussed above, and further discloses wherein
the second area (2nd area of 2nd adhesive, Fig. 7 (61) Murayama) of the second adhesive film of the semiconductor chip (Fig. 7 (60)/(21) of fig 2 embodiment, Murayama)
Murayama does not appear to expressly disclose "the second area of the second adhesive film is larger (obvious) than the area of the semiconductor chip by 20% or more "
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to optimize the adhesive area of the Murayama device. The second adhesive (61) as shown in Fig. 7, is clearly larger than the area of the semiconductor chip by 20% or more given that the die attach film completely seals the semiconductor chip. The DAF seals the chip on the top and bottom of the chip, providing an increased surface area, sealing the chip before dicing. See [col 23, lines 1-2] “The DAF in the lowest layer is needed when the stacked chip sealing bodies are diced into individual pieces.“ [col 12 lines 66-67 and col 13 lines 1-3] “Respective chip sealing bodies are adhered/fixed mutually in the thickness direction by using a die attach film 124 whose thickness is 10 .mu.m to 100 .mu.m.
See [col 23, lines 14-17] “The back surface side of the semiconductor chips located on the opposite side to the integrated circuit surface is sealed by the DAF having a function of the sealing resin.” Thus, the surface area of the DAF includes a resin coving the top of the chip, the sides of the chip and the bottom of the chip. i.e. the DAF is 20% greater or more in area than the chip as shown in Fig. 7.
Furthermore, the Applicant has not shown that an increase in the second area of the second adhesive film by 20% is novel and would not have been found through routine experimentation. Nonetheless, it would have been obvious to one having ordinary skill in the art at the time the invention was made to optimize the area of the 2nd adhesives so as to be able to enhance mechanical stability, and manage thermal and mechanical stresses, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233.)
As to claim(s) 8, Murayama discloses the semiconductor package of claim 7, and further discloses wherein
a thicknesses of the first and second adhesive films
Murayama does not appear to expressly disclose “a sum of thicknesses (obvious) of the first and second adhesive films is 30 μm or more.”
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to optimize the thicknesses of the adhesive area of the Murayama device so as to enhance mechanical stability, manage thermal and mechanical stresses, and provide a uniform, reliable interface for advanced 3D packaging, so as to use an industrially tested and accepted device. Murayama discloses in [col 12 lines 66-67 and col 13 lines 1-3] “Respective chip sealing bodies are adhered/fixed mutually in the thickness direction by using a die attach film 124 whose thickness is 10 .mu.m to 100 .mu.m.”) the second adhesive is already in the range of the claim 8 limitation of 30 μm or more.
Furthermore, the Applicant has not shown the first and second adhesive films thickness of 30 μm or more is novel and would not have been found through routine experimentation. Nonetheless, it would have been obvious to one having ordinary skill in the art at the time the invention was made to optimize the thickness of the adhesives so as to be able to enhance mechanical stability, and manage thermal and mechanical stresses, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233.)
As to claim(s) 9, Murayama discloses the semiconductor package of claim 1, and further discloses wherein
a thicknesses of the first and second adhesive films of the semiconductor chip (chip Fig. 7 (60)/(14) of Fig. 2 embodiment, Murayama).
Murayama does not appear to expressly disclose “a sum of thicknesses (obvious) of the first and second adhesive films is 20% or more of a thickness of the semiconductor chip.”
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to optimize the adhesive area of the Murayama device. The second adhesive (61) as shown in Fig. 7, is clearly larger than the area of the semiconductor chip by 20% or more given that the die attach film completely seals the semiconductor chip. The DAF seals the chip on the top and bottom of the chip, providing an increased surface area, sealing the chip before dicing. See [col 23, lines 1-2] “The DAF in the lowest layer is needed when the stacked chip sealing bodies are diced into individual pieces.“ [col 12 lines 66-67 and col 13 lines 1-3] “Respective chip sealing bodies are adhered/fixed mutually in the thickness direction by using a die attach film 124 whose thickness is 10 .mu.m to 100 .mu.m.
See [col 23, lines 14-17] “The back surface side of the semiconductor chips located on the opposite side to the integrated circuit surface is sealed by the DAF having a function of the sealing resin.” Thus, the surface area of the DAF includes a resin coving the top of the chip, the sides of the chip and the bottom of the chip. i.e. the DAF is 20% greater or more in area than the chip as shown in Fig. 7.
Furthermore, the Applicant has not shown the first and second adhesive films thickness of the of 20% or more of a thickness of the semiconductor chip is novel and would not have been found through routine experimentation. Nonetheless, it would have been obvious to one having ordinary skill in the art at the time the invention was made to optimize the thickness of the adhesives so as to be able to enhance mechanical stability, and manage thermal and mechanical stresses, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233.)
As to claim(s) 15, Murayama discloses the semiconductor package of claim 12, and further discloses wherein
the first and second adhesive structures are implemented as a single adhesive layer
Murayama does not appear to expressly disclose “the first and second adhesive structures are implemented as a single adhesive layer”
Murayama does teach in [col 8 lines 4-11] “The chip stacked body is put on an adhesive layer 66 on a wiring substrate 65, and the end portion of the bonding wire 64 is connected to connection terminals 67 of the wiring substrate 65 respectively. The chip stacked body, the connection terminals on the wiring substrate, and the wiring substrate are sealed with an insulating resin 68, whereby the semiconductor chip stacked body 60 is formed.” This process of forming the staked body 60, as shown in Fig. 7, results in the two adhesive layers being arranged directly adjacent to each other such that they are implemented as a single adhesive layer.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to use the two side-by-side first and second layers adhesive layers of the Murayama device, as a single adhesive primarily to enhance performance, optimize adhesion, and improve thermal conductivity.
As to claim(s) 16, Murayama discloses the semiconductor package of claim 12, and further discloses wherein
a thickness of the second adhesive film is in a range of 10 to 100 μm, and
a sum of thicknesses of the first and second adhesive films is 30 μm or more.
(See Examiner’s Rejections of claims 7 and 8.)
As to claim(s) 17, Murayama discloses the semiconductor package of claim 12, and further discloses wherein
the second adhesive film has a thickness.
Murayama does not appear to expressly disclose “the second adhesive film has a thickness greater (obvious) than a thickness of the first adhesive film.”
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to optimize the adhesive area of the Murayama device. The second adhesive (61) as shown in Fig. 7, is clearly larger than the area of the semiconductor chip by 20% or more, given that the die attach film as shown in Fig. 7, completely seals the semiconductor chip. The DAF seals the chip on the top and bottom of the chip, providing an increased surface area, sealing the chip before dicing. See [col 23, lines 1-2] “The DAF in the lowest layer is needed when the stacked chip sealing bodies are diced into individual pieces.“ [col 12 lines 66-67 and col 13 lines 1-3] “Respective chip sealing bodies are adhered/fixed mutually in the thickness direction by using a die attach film 124 whose thickness is 10 .mu.m to 100 .mu.m.
See [col 23, lines 14-17] “The back surface side of the semiconductor chips located on the opposite side to the integrated circuit surface is sealed by the DAF having a function of the sealing resin.” Thus, the surface area of the DAF includes a resin coving the top of the chip, the sides of the chip and the bottom of the chip. i.e. the DAF is 20% greater or more in area than the chip as shown in Fig. 7.
Claim(s) 6 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Murayama et al. (US 8394678) herein referred to as Murayama in view of Schrock et al. (US 6541872) herein referred to as Schrock.
As to claim(s) 6, Murayama discloses the semiconductor package of claim 1, and further discloses wherein
the first adhesive film (Fig. 7, (66) Murayama)
Murayama does not appear to expressly disclose “a thickness (obvious) of the first adhesive film is in a range of 5 μm to 50 μm.” Schrock discloses an adhesive layer in a range of 5 μm to 50 μm. (“each adhesive layer having a thickness of 0.0005 inches = 12.7 µm”, col 12 lines 32-33 and col 13 lines 1-4, Schrock”).
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to optimize the thicknesses of the adhesive area of the Murayama device such as in the Schrock device so as to enhance mechanical stability, manage thermal and mechanical stresses, and provide a uniform, reliable interface for advanced 3D packaging, so as to use an industrially tested and accepted device.
Furthermore, the Applicant has not shown the first and second adhesive films thickness of 5 μm to 50 μm is novel and would not have been found through routine experimentation. Nonetheless, it would have been obvious to one having ordinary skill in the art at the time the invention was made to optimize the thickness of the adhesives so as to be able to enhance mechanical stability, and manage thermal and mechanical stresses, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233.)
As to claim(s) 10, Murayama discloses the semiconductor package of claim 1, and further discloses wherein
the second adhesive film (61, Murayama) and a first adhesive film (66, Murayama)
Murayama does not appear to expressly disclose “the second adhesive film includes a material the same as that of the first adhesive film”
Schrock teaches the second adhesive film (40, Schrock) includes a material (“the adhesive tape 40 is a hybrid between a thermoplastic and thermoset material. col 8, lines 41-42, Schrock “) the same as that of the first adhesive film (40, “The tape 40 may be a single polymeric adhesive layer or, alternatively, it may be a multi-layer material “, col 6, lines 9-11 Schrock.)
Using the same adhesive film material for two or more layers in a semiconductor device—such as in multi-layer packaging, dicing die bonding (wafer backside protection + die attach), or stacking—is primarily done to optimize process efficiency, ensure structural reliability, and reduce material incompatibility.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the second adhesive film and the first adhesive film of the same material, so as to optimize process efficiency, ensure structural reliability, and reduce material incompatibility ensuring an industrially tested and accepted devices/material.)
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN SHAW MUSLIM whose telephone number is (571)270-0071. The examiner can normally be reached Mon-Fri 7 am - 4 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on (571) 272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897