DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species VI as shown in Fig. 16, and claims 1-6 and 11-26 in the reply filed on 12/17/2025 is acknowledged.
Claims 7-10 were withdrawn by the applicant from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/17/2025.
Information Disclosure Statement
Acknowledgement is made of Applicant's Information Disclosure Statement (IDS) from PTO-1449. The IDS has been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a).
Claim 21 recites the limitation wherein “the optical element comprises at least one of an intra-layer lens, a color filter, and a microlens.” The drawings must show every feature of the invention specified in the claims. Therefore, the features recited in the claim must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. (US 2017/0207158 A1).
Re Claim 1, Kang teaches a semiconductor device (Fig. 6B) in which a first semiconductor layer (101, Fig. 6B, para [0021]), a second semiconductor layer (201, Fig. 6B, para [0033]), and a third semiconductor layer (301, Fig. 6B, para [0045]) are stacked (see Fig. 6B), wherein
the second semiconductor layer (201) is arranged (see Fig. 6B) between the first semiconductor layer (101) and the third semiconductor layer (301),
a first structure (142+143+144+145, Fig. 6B, para [0021]) comprising a first insulating layer (142) is arranged between a first principal surface of the first semiconductor layer (top surface of 101) and a second principal surface of the second semiconductor layer (bottom surface of 201), which face each other (see Fig. 6B),
a second structure (241, Fig. 6B, para [0033]) comprising a second insulating layer (241) is arranged between a third principal surface of the second semiconductor layer (top surface of 201) and a fourth principal surface of the third semiconductor layer (bottom surface of 301), which face each other,
in an orthographic projection to the fourth principal surface (bottom surface of 301), a region where a plurality of elements (303+310, Fig. 6B, paras [0045] – [0046]) are arranged in the third semiconductor layer (301) is defined as a first region (cell area CA, Fig. 6B, para [0021]), and a region between the first region and a peripheral portion of the third semiconductor layer is defined as a second region (peripheral area PA, Fig. 6B, para [0021]),
in the second region (PA region), an opening portion (opening hole, “H”, Fig. 6B, para [0096]) configured to expose a pad electrode (173, Fig. 6B, para [0021]) arranged in the first structure (142+143+144+145) is arranged (see Fig. 6B),
the opening portion (opening hole, “H”, Fig. 6B) extends through the third semiconductor layer (301), the second structure (241), and the second semiconductor layer (201) from a fifth principal surface of the third semiconductor layer (top surface of 301), on an opposite side of the fourth principal surface (bottom surface of 301) to the pad electrode (173), and
between the first insulating layer (142) and the second insulating layer (241) and between the first region (cell area CA) and the opening portion (opening hole, “H”), an insulator portion (280, Fig. 6B, para [0033]) is arranged at the same height (see Fig. 6B) as the second semiconductor layer (201).
Re Claim 2, Kang teaches the device according to claim 1, wherein in an orthographic projection to the third principal surface (top surface of 201), the insulator portion (280) is arranged to surround the opening portion (280 surrounds the opening in the plan-view, see Fig. 2A and compare to Figs. 1F and 6B, para [0065]).
Re Claim 3, Kang teaches the device according to claim 2, wherein the insulator portion (280) forms a wall surface of a portion of the opening portion (opening hole, “H”, see Fig. 6B) extending through the second semiconductor layer (201).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 2017/0207158 A1) as applied to claim 3 above, and further in view of Jang et al. (US 2023/0081238 A1).
Re Claim 4, Kang teaches the device according to claim 3, wherein in the orthographic projection to the third principal surface (top surface of 201), the insulator portion (208) is arranged continuously for the opening portion (280 continuously surrounds the opening in the plan-view, see Fig. 2A and compare to Figs. 1F and 6B, para [0065]).
Kang does not explicitly teach a plurality of pad electrodes and a plurality of opening portions.
Related art Jang teaches that there can be plurality of pad portions (PAD, Fig. 1) in the peripheral area, and have a corresponding pad electrode (480, Fig. 11, para [0078]) and an opening portion (pad opening 480H, Fig. 11, para [0078]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, there can be a plurality of pad portions for multiple connections to the pixel area in the device of Kang as taught by Jang, and thus the insulator portion (280, Fig. 2A, Kang) is arranged continuously for the plurality of opening portions (280 continuously surrounds each of the plurality openings, Fig. 2A, Kang).
Re Claim 5, Kang teaches the device according to claim 3, wherein
in the orthographic projection to the third principal surface (top surface of 201), the insulator portion (280) includes a first portion surrounding the first opening portion (280 continuously surrounds the opening in the plan-view, see Fig. 2A and compare to Figs. 1F and 6B, para [0065]).
Kang does not explicitly teach a plurality of pad electrodes and a plurality of opening portions.
Related art Jang teaches that there can be plurality of pad portions (PAD, Fig. 1) in the peripheral area, and have a corresponding pad electrode (180, Fig. 2, para [0051]) and an opening portion (pad opening 180H, Fig. 2, para [0051]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, there can be a plurality of pad portions for multiple connections to the pixel area in the device of Kang as taught by Jang.
Thus, Kang modified by Jang teaches:
the plurality of opening portions include a first opening portion and a second opening portion, which are adjacent to each other (multiple PAD portions which are adjacent to each other, see Fig. 1, Jang),
in the orthographic projection to the third principal surface (top surface of 201, Kang), the insulator portion (280, Fig. 2A, Kang) includes a first portion surrounding the first opening portion, and a second portion surrounding the second opening portion (each insulator portions 280 surround each of the plurality of openings, including a first and a second opening portion, see Fig. 2A of Kang in view of Fig. 1 of Jang), and
a part of the second semiconductor layer is arranged between the first portion and the second portion (each PAD portions, including each of the insulator portions 280 form an isolated island, see Fig. 2A of Kang in view of Fig. 1 of Jang, separated by a part the second substrate 201 of Kang, marked “connection part” in annotated figure below).
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Re Claim 6, Kang modified by Jang teaches the device according to claim 5, wherein a portion of the second semiconductor layer arranged in the first region (portion of 201 in CA region, Fig. 6B, Kang) and a portion of the second semiconductor layer arranged between the plurality of opening portions and a peripheral portion of the second semiconductor layer (portion of 201 along the peripheral edge boundary, Fig. 6B, Kang) continues via the part of the second semiconductor layer (“connection part” of the substrate, see annotated figure above).
Rejection 2
Claims 1, 11, 14-15, 20 and 22 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jang et al. (US 2023/0081238 A1).
Re Claim 1, Jang teaches a semiconductor device (Fig. 12) in which a first semiconductor layer (130, Fig. 12, para [0033]), a second semiconductor layer (120, Fig. 12, para [0033]), and a third semiconductor layer (110, Fig. 12, para [0033]) are stacked, wherein
the second semiconductor layer (120) is arranged between the first semiconductor layer (130) and the third semiconductor layer (110),
a first structure (BS1+FS3, Fig. 12, para [0031]) comprising a first insulating layer (132, Fig. 12, para [0036]) is arranged between a first principal surface of the first semiconductor layer (top surface of 130) and a second principal surface of the second semiconductor layer (bottom surface of 120), which face each other (see Fig. 12),
a second structure (FS1+FS2, Fig. 12, para [0031]) comprising a second insulating layer (121+122+123, Fig. 12, para [0035]) is arranged between a third principal surface of the second semiconductor layer (top surface of 120) and a fourth principal surface of the third semiconductor layer (bottom surface of 110), which face each other (see Fig. 12),
in an orthographic projection to the fourth principal surface (bottom surface of 110), a region where a plurality of elements (plurality of photodiodes, PD, Figs. 5 and 12, para [0063]) are arranged in the third semiconductor layer (110) is defined as a first region (active region APR, Fig. 12, para [0027]), and a region between the first region and a peripheral portion of the third semiconductor layer is defined as a second region (pad region PDR, Fig. 12, para [0027]),
in the second region (pad region PDR), an opening portion (marked “opening hole” in annotated Fig. 12 below, para [0085]) configured to expose a pad electrode (580, Fig. 12, para [0086]) arranged in the first structure (BS1+FS3) is arranged,
the opening portion (“opening hole”, Fig. 12) extends through the third semiconductor layer (110), the second structure (FS1+FS2), and the second semiconductor layer (120) from a fifth principal surface of the third semiconductor layer (top surface of 110), on an opposite side of the fourth principal surface (bottom surface of 110) to the pad electrode (580), and
between the first insulating layer (132) and the second insulating layer (121+122+123) and between the first region (APR region) and the opening portion (“opening hole”), an insulator portion (marked “insulator portion” in annotated Fig. 12 below) is arranged at the same height (see Fig. 12) as the second semiconductor layer (120).
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Re Claim 11, Jang teaches the device according to claim 1, wherein a conductive member (129, Fig. 12, para [0052]) extending through the second semiconductor layer (120) from the first structure (BS1+FS3) to the second structure (FS1+FS2) is further arranged in the second region (PDR region).
Re Claim 14, Jang teaches the device according to claim 1, wherein the plurality of elements include a photoelectric conversion element (photodiode, PD, Fig. 12, para [0063]).
Re Claim 15, Jang teaches the device according to claim 14, wherein an element circuit comprising a transistor (pixel gate PXT constituting a pixel circuit, Fig. 12, para [0045]) configured to amplify a signal output from the photoelectric conversion element (acts as an amplifier, para [0047]) is arranged on the second principal surface (bottom surface of 120, Fig. 12), and
a driving circuit (LCT, Fig. 12, para [0029]) configured to drive the plurality of elements and the element circuit (para [0029]) is arranged on the first principal surface (top surface of 130, Fig. 12).
Re Claim 20, Jang teaches the device according to claim 14, wherein a third structure (182+ML+CF, Fig. 12, paras [0031] and [0057]) including an optical element (ML+CF, Fig. 12, para [0031]) is further arranged on the fifth principal surface (top surface of 110).
Re Claim 22, Jang teaches the device according to claim 20, wherein the opening portion (“opening hole”, Fig. 12) further extends through the third structure (182+ML+CF), and
in an orthographic projection to the fifth principal surface (top surface of 110), a portion of the opening portion extending through the third semiconductor layer (110), the second structure (FS1+FS2), and the second semiconductor layer (120) is arranged (see Fig. 12) inside a portion of the opening portion arranged in the third structure (182+ML+CF).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found earlier in this Office action.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 2023/0081238 A1) as applied to claim 11 above, and further in view of Kobayashi et al. (US 2013/0105667 A1).
Re Claim 12, Jang teaches the device according to claim 11, but does not disclose that the conductive member is arranged to surround the first region.
However, in a related art, Kobayashi teaches that the conductive members in the peripheral regions (150A+151A+152A+150B, Fig. 4, para [0045]) can form a plurality of seal rings (para [0045]), which can surround the active region (Fig. 3A, 150A surrounds the active region, para [0048]). The seal rings are provided to reduce water from entering inside the device (para [0045]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to form seal rings from the conductive structures in the device Jang, as taught by Kobayashi, such that it surrounds the active region and prevents water from entering inside the device (para [0045], Kobayashi).
Re Claim 13, Jang teaches the device according to claim 11, but does not disclose that the conductive member is arranged to surround the opening portion.
However, in a related art, Kobayashi teaches that the conductive members in the peripheral regions (150A+151A+152A+150B, Fig. 4, para [0045]) can form a plurality of seal rings (para [0045]), which can surround the opening pad portion (Fig. 3A, 151A surrounds the opening pad portion, para [0049]). The seal rings are provided to reduce water from entering inside the device (para [0045]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to form seal rings from the conductive structures in the device Jang, as taught by Kobayashi, such that it surrounds the opening pad portion and prevents water from entering inside the device (para [0045], Kobayashi).
Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 2023/0081238 A1) as applied to claim 15 above, and further in view of Saka et al. (US 2022/0367540 A1).
Re Claim 16, Jang teaches the device according to claim 15, wherein the insulator portion (“insulator portion”, see claim 1 above) is defined as a first insulator portion,
the first structure (BS1+FS3) comprises a wiring pattern (137, Fig. 12, para [0036]) arranged in the first insulating layer (132),
a plug electrode (marked “plug electrode” in annotated Fig. 12 below, para [0052]) configured to connect the photoelectric conversion element (photodiode, PD) and the wiring pattern (137) is arranged to extend through the second structure (FS1+FS2) and the second semiconductor layer (120), and
a second insulator portion (marked “2nd insulator portion” in annotated Fig. 12 below, which fills the through hole 120H, para [0072]) surrounding the plug electrode (“plug electrode”) and extending through the second semiconductor layer (120) from the second principal surface (bottom surface of 120) to the third principal surface (top surface of 120) is arranged in the second semiconductor layer (120).
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Jang does not show a top view for the second semiconductor substrate 120 and hence does not explicitly show that “in the orthographic projection to the third principal surface, a second insulator portion surrounding the plug electrode”. However, as stated above, the second insulator portion (marked “2nd insulator portion” in annotated Fig. 12 above) fills the through hole 120H (Fig. 12, para [0072]) surrounding the plug electrode (“plug electrode”) and hence it would be obvious to one of ordinary skill in the art, that the second insulator portion completely surrounds the “plug electrode” in a top -view, to completely isolate the electrode and avoid any cross-talk or electrical miscommunication. Additionally, related art Saka also shows a similar plug electrode (TGV, Fig. 6, para [0153]) in the second substrate 200S (Fig. 6) surrounded by an insulator portion (212, Fig. 6) in a top view (212, Fig. 9), performing a similar function.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the second insulator portion would surround the plug electrode in a top view in the device of Jang, because that would completely isolate the electrode and avoid any cross-talk or electrical miscommunication. This is also shown by related art Saka, performing a similar function. The use of a known interconnection structure for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Re Claim 17, Jang modified by Saka teaches the device according to claim 16, wherein the first insulator portion (“insulator portion”, Jang) and the second insulator portion (“2nd insulator portion”, Jang) are made of the same material (both are part of the same material layer, see Fig. 12, Jang).
Re Claim 18, Jang modified by Saka teaches the device according to claim 16, wherein the second insulating layer (121+122+123, Fig. 12, Jang) includes a first layer (121+122) that is in contact with the second semiconductor layer (120), and a second layer (123) that is arranged between the first layer (121+122) and the third semiconductor layer (110) and is in contact with the first layer (121+122),
and the second layer (123 can be silicon nitride, para [0035], Jang) is made of a material different from the second insulator portion (“2nd insulator portion” is part of layers 121/124, Fig. 12, which are made of silicon oxide, para [0035], Jang).
Re Claim 19, Jang modified by Saka teaches the device according to claim 18, wherein the second insulator portion is made of silicon oxide (“2nd insulator portion” is part of layers 121/124, Fig. 12, which are made of silicon oxide, para [0035], Jang), and the second layer is made of silicon nitride or polycrystalline silicon (123 can be silicon nitride, para [0035], Jang).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 2023/0081238 A1) as applied to claim 20 above, and further in view of Ogawa et al. (US 2020/0127030 A1).
Re Claim 21, Jang teaches the device according to claim 20, wherein the optical element comprises at least one of a color filter and a microlens (ML+CF, Fig. 12, para [0031]).
Jang does not disclose an intra-layer lens.
In a related semiconductor art, Ogawa teaches that there can be an additional intra-layer lens (31, Fig. 3B, para [0062]), in addition to the microlens and color filer (70+80, Fig. 3B, para [0034]), which is useful to reduce color mixing and improving light-shielding performance (para [0063]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to include the intralayer lens into the device structure of Jang as taught by Ogawa, as it is useful to reduce color mixing and improving light-shielding performance (para [0063], Ogawa).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 2023/0081238 A1) as applied to claim 1 above, and further in view of Huang et al. (US 2022/0231067 A1) and Kurokawa et al. (US 2015/0296162 A1).
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Re Claim 26, Jang teaches the device according to claim 1, wherein in the orthographic projection to the third principal surface (top surface of 120),
the second semiconductor layer (120) has a rectangular shape (see Fig. 1), and
a width of a region (marked “w1” in annotated Fig. 1 below) of the second region (pad region PDR) where the insulator portion is arranged (“insulator portion”),
a length of a short side of the second semiconductor layer (width of layer 102 in Fig. 1).
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Jang shows that the width of a region (marked “w1” in annotated Fig. 1 below) of the second region (pad region PDR) where the insulator portion is arranged is smaller than a length of a short side of the second semiconductor layer (width of layer 102 in Fig. 1), but does not explicitly state it is smaller by 1/100 or less.
Related art Huang teaches a length of a similar pad region as Jang and discloses that the pad length (102p, Fig. 5), can be between 5-50 µm (para [0040]). Additional art, Kurokawa teaches that a typical die size for an image sensor is 6.5 mm × 6.0 mm (para [0462]), which would be equivalent to the size of the substrate layer of Jang. From the teachings of Huang and Kurokawa, a ratio of a width of the second region of Jang to a length of a short side of the second semiconductor layer of Jang, would be 50 µm / 6.0 mm = 0.83/100, within the claimed range. It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the ratio and arrive at the claimed range. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed range would have been obvious to one of ordinary skill in the art.
Allowable Subject Matter
Claims 23-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 23 is allowable for at least the reasons of, “a maximum oxygen concentration in the first semiconductor layer is higher than a maximum oxygen concentration in the second semiconductor layer, and the maximum oxygen concentration in the second semiconductor layer is higher than a maximum oxygen concentration in the third semiconductor layer”. This limitation is neither anticipated nor made obvious by the prior art of record in the Examiner’s opinion.
Regarding Claim 23, Jang et al. (US 2023/0081238 A1) teaches that the first, second and third substrate layers are made of silicon (para [0033]), but does not disclose anything about oxygen concentration within the substrate. Related arts, Hongo et al. (US 2016/0035766 A1), Hirota et al. (US 2021/0126026 A1) and Ikeda et al. (US 2020/0176493 A1) teach that there can be oxygen impurity acting as defects (paras [0030] – [0031], Hongo) or dopants (para [0024], Hirota) within the silicon substrate, or the oxygen impurity can be adjusted for obtaining specific semiconductor characteristics of the transistor (para [0170], Ikeda). However, they do not disclose the above recited limitations.
Claim 24 is allowable for at least the reasons of, “a maximum oxygen concentration in the second semiconductor layer is higher than a maximum oxygen concentration in the first semiconductor layer and a maximum oxygen concentration in the third semiconductor layer”. This limitation is neither anticipated nor made obvious by the prior art of record in the Examiner’s opinion.
Regarding Claim 24, Jang et al. (US 2023/0081238 A1) teaches that the first, second and third substrate layers are made of silicon (para [0033]), but does not disclose anything about oxygen concentration within the substrate. Related arts, Hongo et al. (US 2016/0035766 A1), Hirota et al. (US 2021/0126026 A1) and Ikeda et al. (US 2020/0176493 A1) teach that there can be oxygen impurity acting as defects (paras [0030] – [0031], Hongo) or dopants (para [0024], Hirota) within the silicon substrate, or the oxygen impurity can be adjusted for obtaining specific semiconductor characteristics of the transistor (para [0170], Ikeda). However, they do not disclose the above recited limitations. Claim 25 depends from claim 24 and is allowable for at least the reasons above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898