Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10-16, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al. (US 2019/0131225 A1).
Regarding independent claim 10: Jeong teaches (e.g., Figs. 4A-4K) a support structure, comprising
a conductive metal feature ([0064]: 122c) with an attachment location (Fig. 4G; [0064]: top surface of 122c); and
bond wires ([0047]: layers P are bond wires) on the attachment location.
Regarding claim 11: Jeong teaches the claim limitation of the support structure of claim 10, on which this claim depends,
wherein each bond wire has a first end (Fig. 4G; [0047]: left side layer P) with a first bond ([0065]: left side bond 115) connected to a first portion of the attachment location (left side portion), and
a second end (Fig. 4G; [0047]: layers P are bond wires) with a second bond ([0065]: right side bond 115) connected to a second portion of the attachment location (right side portion).
Regarding claim 13: Jeong teaches the claim limitation of the support structure of claim 12, on which this claim depends,
wherein first and second ones of the bond wires overlap one another (Jeong: Fig.3; [0047]: bond wires P overlap each other).
Regarding claim 14: Jeong teaches the claim limitation of the support structure of claim 11, on which this claim depends,
wherein first and second ones of the bond wires overlap one another (Jeong: Fig.3; [0047]: bond wires P overlap one another).
Regarding claim 15: Jeong teaches the claim limitation of the support structure of claim 10, on which this claim depends,
wherein first and second ones of the bond wires overlap one another (Jeong: Fig.3; [0047]: bond wires P overlap one another).
Regarding claim 16: Jeong teaches the claim limitation of the support structure of claim 10, on which this claim depends,
support structure is a multilevel package substrate having first and second levels in respective first and second planes of orthogonal first and second directions in a stack along a third direction Z that is orthogonal to the first and second directions, the first level including the conductive metal feature.
Regarding independent claim 18: Jeong teaches (e.g., Fig. 3 and Figs. 4A-4I) a method of fabricating an electronic device, the method comprising:
forming bond wires ([0047]: layers P are bond wires) on an attachment location of a conductive feature of a support structure ([0036]: 120);
soldering a conductive terminal ([0043] and [0065]: 115 is used to solder a conductive terminal 112B) of a semiconductor die ([0043]: 112) to the attachment location of the conductive feature over at least some of the bond wires (Fig. 4H; P).
Regarding claim 20: Jeong teaches the claim limitation of the method of claim 18, on which this claim depends.
wherein forming the bond wires includes overlapping first and second ones of the bond wires (Jeong: Fig.3; [0047]: bond wires P overlap each other).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US 2019/0131225 A1) in view of Seo et al. (US 2017/0338206 A1).
Regarding independent claim 1: Jeong teaches (e.g., Fig. 3) an electronic device, comprising:
a semiconductor die ([0036]: 100A) having: a semiconductor body ([0036]: 112);
over the semiconductor body (112); and
a conductive terminal ([0043]: 112B),
the conductive terminal (112B) extending away from the plane along a third direction that is orthogonal to the first and second directions; and
a support structure ([0036]: 120) having a conductive metal feature ([0036] and [0039]: 122/123) with an attachment location (uppermost location of 122); and
bond wires ([0047]: layers P are bond wires) on the attachment location; and
a package structure ([0036]: 160) that at least partially encloses the semiconductor die and a portion of the support structure (120);
wherein the conductive terminal (112B) is soldered to the attachment location of the conductive feature (122/123) over at least some of the bond wires (P).
Jeong does not expressly teach
a metallization structure over the semiconductor body and the metallization structure including a top level that extends in a plane of orthogonal first and second directions.
Seo teaches (e.g., Figs. 1A-1D) an electronic device, comprising:
a metallization structure (Fig. 1D; [0036] and [0038] and [0051]: 112/220 corresponds to 112/120) over a semiconductor body ([0049]: 210) and the metallization structure including a top level (portion 114/124) that extends in a plane of orthogonal first and second directions (Fig. 1; plane of orthogonal first and second directions x-direction and y-direction respectively)
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Jeong, the metallization structure over the semiconductor body and the metallization structure including a top level that extends in a plane of orthogonal first and second directions, as taught by Seo, for the benefits of increasing integrate circuit density and functionalities by creating inner wiring connecting the internal devices and outer devices.
Regarding claim 2: Jeong and Seo teach the claim limitation of the electronic device of claim 1, on which this claim depends,
wherein the support structure is a multilevel package substrate (Jeong: [0036], [0039] and [0044]: 120 comprises a stack of insulating layers 121 and conductive metal features 123 and 122 this constitutes a multilevel package substrate; thus meets the claim limitation requirement) having first and second levels in respective first and second planes of the first and second directions (Jeong: Fig. 3; X-direction and Y-direction) in a stack along the third direction Z (Jeong: Fig. 3; vertical direction), the first level including the conductive metal feature (Jeong: [0036], [0039] and [0044]: conductive metal features 123 and 122).
Regarding claim 3: Jeong and Seo teach the claim limitation of the electronic device of claim 2, on which this claim depends,
wherein first and second ones of the bond wires overlap one another (Jeong: Fig.3; [0047]: bond wires P overlap each other).
Regarding claim 8: Jeong and Seo teach the claim limitation of the electronic device of claim 1, on which this claim depends,
wherein first and second ones of the bond wires overlap one another Jeong: Fig.3; [0047]: bond wires P overlap each other).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US 2019/0131225 A1) in view of Seo et al. (US 2017/0338206 A1) as applied above and further in view of Fuji (US 2021/0280551 A1).
Regarding claim 9: Jeong and Seo teach the claim limitation of the electronic device of claim 1, on which this claim depends,
Jeong as modified by Seo does not expressly teach wherein the attachment location of the conductive metal feature has a roughened surface.
Fuji teaches (e.g., Figs. 1-2 and 8) an electronic device comprising a conductive metal feature (([0071]-[0073] and [0076]: 92);
Fuji further teaches that an attachment location ([0071]-[0072] and [0076]; [0099]-[0101]): 92a) of the conductive metal feature has a roughened surface ([0099]-[0101]).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Jeong as modified by Seo and Zhang, the attachment location of the conductive metal feature having a roughened surface, as taught by Fuji, for the benefits of increasing bonding and adhesion strength, thus reducing possibility of delamination of in interconnection structure, which in turn improve device reliability.
Claims 4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US 2019/0131225 A1) in view of Seo et al. (US 2017/0338206 A1) as applied above and further in view of Zhang et al. (US 2020/0365505 A1).
Regarding claim 4: Jeong and Seo teach the claim limitation of the electronic device of claim 1, on which this claim depends,
Jeong as modified by Seo does not expressly teach that the support structure is a lead frame that includes the conductive metal feature.
Zhang teaches (e.g., Fig. 1) an electronic device comprising a support structure ([0028]: 20);
Zhang further teaches that the support structure is a lead frame ([0028]: 20) that includes a conductive metal layer ([0028]-[0029]).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Jeong as modified by Seo, the support structure being a lead frame, as taught by Zhang, for the benefits of improving heat dissipation of the device in operation because of the thermal conduction capability of the lead-frame, thus reducing the possibility of device warping or damage, which in turn improves device reliability.
Regarding claim 7: Jeong, Seo and Zhang teach the claim limitation of the electronic device of claim 4, on which this claim depends,
wherein first and second ones of the bond wires overlap one another Jeong: Fig.3; [0047]: bond wires P overlap each other).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US 2019/0131225 A1) in view of Seo et al. (US 2017/0338206 A1) and Zhang et al. (US 2020/0365505 A1) as applied above and further in view of Fuji (US 2021/0280551 A1).
Regarding claim 5: Jeong, Seo and Zhang teach the claim limitation of the electronic device of claim 4, on which this claim depends,
Jeong, Seo and Zhang teach the claim limitation the attachment location of the conductive metal feature has a roughened surface.
Fuji teaches (e.g., Figs. 1-2 and 8) an electronic device comprising a conductive metal feature ([0071]-[0073]: 92);
Fuji teaches that an attachment location ([0071]-[0072] and [0076]; [0099]-[0101]: 92a) of the conductive metal feature has a roughened surface ([0072] and [0076]; [0099]-[0101]).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Jeong as modified by Seo and Zhang, the attachment location of the conductive metal feature having a roughened surface, as taught by Fuji, for the benefits of increasing bonding and adhesion strength, thus reducing possibility of delamination of in interconnection structure, which in turn improve device reliability.
Regarding claim 6: Jeong, Seo, Zhang and Fuji teach the claim limitation of the electronic device of claim 5, on which this claim depends,
wherein first and second ones of the bond wires overlap one another Jeong: Fig.3; [0047]: bond wires P overlap each other).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US 2019/0131225 A1) in view of Fuji (US 2021/0280551 A1).
Regarding claim 12: Jeong teaches the claim limitation of the support structure of claim 11, on which this claim depends,
Jeong does not expressly teach that the attachment location of the conductive metal feature has a roughened surface.
Fuji teaches (e.g., Figs. 1-2 and 8) a support structure comprising a conductive metal feature ([0071]-[0073], [0076]; [0097] and [0102]: 92);
Fuji further teaches that an attachment location ([0071]-[0072] and [0076]; [0097]-[0101]: 92a) of the conductive metal feature has a roughened surface ([0071]-[0072] and [0076]; [0099]-[0101]).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Jeong as modified by Seo and Zhang, the attachment location of the conductive metal feature having a roughened surface, as taught by Fuji, for the benefits of increasing bonding and adhesion strength, thus reducing possibility of delamination of in interconnection structure, which in turn improve device reliability.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US 2019/0131225 A1) in view of Zhang et al. (US 2020/0365505 A1).
Regarding claim 17: Jeong teaches the claim limitation of the support structure of claim 10, on which this claim depends,
wherein the support structure is a lead frame.
Jeong does not expressly teach that the support structure is a lead frame that includes the conductive metal feature.
Zhang teaches (e.g., Fig. 1) an electronic device comprising a support structure ([0028]: 20);
Zhang further teaches that the support structure is a lead frame ([0028]: 20) that includes a conductive metal layer ([0028]-[0029]).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Jeong, the support structure being a lead frame, as taught by Zhang, for the benefits of improving heat dissipation of the device in operation because of the thermal conduction capability of the lead-frame, thus reducing the possibility of device warping or damage, which in turn improves device reliability.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US 2019/0131225 A1) in view of Fuji (US 2021/0280551 A1).
Regarding claim 19: Jeong teaches the claim limitation of the method of claim 18, on which this claim depends.
Jeong does not expressly teach that the method further comprises roughening a surface of the attachment location of a conductive feature before forming the bond wires.
Fuji teaches (e.g., Figs. 1-2 and 8) a method of forming an electronic device comprising a conductive metal feature ([0071]-[0072] and [0076]: 92);
Fuji further teaches that the method comprises roughening a surface of the attachment location of a conductive feature ([0071]-[0072] and [0076]; [0099]-[0101]: roughening attachment location 92a) before forming the bond wires.
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Jeong as modified by Seo and Zhang, the method of roughening a surface of the attachment location of a conductive feature before forming the bond wires, as taught by Fuji, for the benefits of increasing bonding and adhesion strength, thus reducing possibility of delamination of in interconnection structure, which in turn improve device reliability.
Response to Arguments
Applicant's arguments filed 02/04/2026 have been fully considered but they are not persuasive.
Applicant argued that Jeong does not teach the limitation “bond wires on the attachment location” because Jeong does not use the terminology expected or bond wire.
However, the reference applied does not have to use the same terminology to teach a limitation of the instant application.
Applicant further stated that Jeong use the terminology of redistribution layer instead of bond wire. However, the element P of Jeong is not considered a redistribution layer. Applicant does not include enough specificity to exclude the use of Jeong.
Indeed, in a rigorous treatment of the term “bond wire”, which is a term of art and has a specific meaning and specific use, the bond wire as the name suggest is a wire, and as used in the technology, it means literally a wire. This wire is used not at the interface of a pad of a chip, but for interconnecting the chip to a distant conductive structure, as an interconnect; therefore, the term “bond wire” appears to be misused in this context. Bond wires are used for a different type of connection technology. Based on this, Examiner mapped the claim limitations with the understanding that the term “bond wire” is used to mean a conductive layer, as is well known in the art.
As for the word attachment location, there is no special definition, any location or area intended to be used for a layer is considered as an attachment location.
Furthermore, Applicant, argued that Examiner, has used a piecemeal rejection for the obviousness rejections.
In response to applicant's argument that the references have been used in a piecemeal manner, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Additionally, in response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Examiner recognized that one of ordinary skill in the art would have a motivation that is different from the Applicants own motivation.
Therefore, Examiner concludes that the rejection of the all the claims as shown above, is proper.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812