DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant’s arguments, see page 9, filed 04/24/2026, with respect to the rejections of claims 11-15 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of Tseng et al. (US 20190221639 A1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US 20210280716 A1; hereinafter Peng) in view of Tseng et al. (US 20190221639 A1; hereinafter Tseng).
Regarding claim 11, FIG. 1A-1C of Peng teach a semiconductor device (102B ¶ [0023]), comprising: channels (122) spaced apart from each other on a substrate (106) in a vertical direction substantially perpendicular to an upper surface of the substrate (Z direction ¶ [0026]); a gate structure (112B) on the substrate (106 ¶ [0025]), the gate structure (112B) bordering lower and upper surfaces and a first sidewall of at least a portion of each of the channels (surfaces of 122 ¶ [0026]); a source/drain layer (110B) on a portion of the substrate (106) adjacent to the gate structure (112B), the source/drain layer (110B) contacting second sidewalls of the channels (sidewalls of 112B ¶ [0025]-[0026]); and an oxide pattern (uppermost 113B, hereinafter ‘113B’ ¶ [0025],[0043]) contacting an upper surface of an end portion of an uppermost one of the channels (upper surface of an end portion of uppermost instance of 122), an upper surface of the oxide pattern (upper surface of 113B) being lower than an upper surface of the source/drain layer (upper surface of 110B), and the oxide pattern (113B) including silicon oxynitride (¶ [0043]).
Peng does not teach the oxide pattern including silicon oxynitride.
FIG. 12 of Tseng teaches CMOS transistor structure (80, 90 ¶ [0040]) comprising an oxide pattern (134, 136 ¶ [0048]) contacting an end portion of an uppermost channel (end portion of uppermost 102, 104 ¶ [0041]-[0042]), and the oxide pattern (134, 136) including silicon oxynitride (¶ [0048]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Peng with the oxide pattern taught by Tseng for the purpose of efficient formation of the oxide pattern, supporting the channel structure (¶ [0031]), and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Regarding claim 12, Peng as modified teaches the semiconductor device as claimed in claim 11, and FIGS. 1A-1C of Peng further teach further comprising a gate spacer (114B ¶ [0025]) on an upper sidewall of the gate structure (upper sidewall of 112B), wherein the oxide pattern (113B) is interposed between the uppermost one of the channels (uppermost 122) and the gate spacer (114B, see FIG. 1C).
Regarding claim 13, Peng as modified teaches the semiconductor device as claimed in claim 11, and FIGD. 1A-1C of Peng teach wherein the oxide pattern (113B) does not overlap the gate structure (112B) in the vertical direction (Z direction).
Regarding claim 14, Peng as modified teaches the semiconductor device as claimed in claim 13, and FIGS. 1A-1C of Peng teach wherein a sidewall of the oxide pattern (113B) contacts the gate structure (112B).
Regarding claim 15, Peng as modified teaches the semiconductor device as claimed in claim 11, and FIG. 1C of Peng according to another interpretation further teaches wherein a portion of the oxide pattern (113B) overlaps the gate structure (112B, 114B) in the vertical direction (Z direction).
Allowable Subject Matter
Claims 1-10 and 16-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 1 recites a semiconductor device, comprising: channels spaced apart from each other on a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate; a gate structure on the substrate, the gate structure bordering lower and upper surfaces and a first sidewall of at least a portion of each of the channels; and a source/drain layer on a portion of the substrate adjacent to the gate structure, the source/drain layer contacting second sidewalls of the channels, wherein a nitrogen-containing portion is formed at an upper portion of an uppermost one of the channels, the nitrogen-containing portion being doped with nitrogen, and wherein the nitrogen-containing portion is positioned between portions of the gate structure disposed on the upper portion of the uppermost one of the channels.
FIG. 1 of Chen et al. (US 20210367032 A1; hereinafter Chen) teaches a semiconductor device (e.g. FIG. 20), comprising: channels (135) spaced apart from each other on a substrate (120) in a vertical direction substantially perpendicular to an upper surface of the substrate (Z direction); a gate structure (145) on the substrate (120), the gate structure (145) bordering lower and upper surfaces and a first sidewall of at least a portion of each of the channels (surfaces of 135); and a source/drain layer (110) on a portion of the substrate (120) adjacent to the gate structure (145), the source/drain layer (110) contacting second sidewalls of the channels (sidewalls of 135), wherein a nitrogen-containing portion (portion of an uppermost instance of 150, hereinafter ‘150’) is formed at an upper portion of an uppermost one of the channels (upper portion of uppermost instance of 135), and wherein the nitrogen-containing portion (150) is positioned between portions of the gate structure (portions of 145) disposed on the upper portion of the uppermost one of the channels (upper portion of uppermost 135).
However, the prior art fails to teach or reasonably suggest “the nitrogen-containing portion being doped with nitrogen” together with all the limitations of claim 1 as claimed. Claims 1-10 are allowable insofar as they depend upon and require all the limitations of claim 1.
Claim 16 recites a semiconductor device, comprising: an active pattern on a substrate; channels spaced apart from each other on the active pattern in a vertical direction substantially perpendicular to an upper surface of the substrate; a gate structure on the substrate, the gate structure bordering lower and upper surfaces and a first sidewall of at least a portion of each of the channels; a source/drain layer on a portion of the substrate adjacent to the gate structure, the source/drain layer contacting second sidewalls of the channels; a gate spacer on an upper sidewall of the gate structure; a nitrogen-containing portion along an upper portion of an uppermost one of the channels; and an oxide pattern between an upper surface of each of opposite end portions of the uppermost one of the channels and a lower surface of the gate spacer, wherein a portion of the gate structure is positioned along the upper surface and between the nitrogen-containing portion and the oxide pattern.
FIGS. 2A-D of Cheng et al. (US 20210320191 A1; hereinafter Cheng) teach a semiconductor device (e.g. FIG. 2A), comprising: an active pattern (11) on a substrate (10 ¶ [0048]); channels (20) spaced apart from each other on the active pattern (11) in a vertical direction substantially perpendicular to an upper surface of the substrate (Z direction ¶ [0048]); a gate structure (108, 106) on the substrate (10), the gate structure (108, 106) bordering lower and upper surfaces and a first sidewall of at least a portion of each of the channels (lower and upper surfaces of 20 in Z direction, sidewalls of 20 in Y direction, see FIG. 2B ¶ [0049]); a source/drain layer (80, 85) on a portion of the substrate (10) adjacent to the gate structure (108, 106 ¶ [0050]), the source/drain layer (80, 85) contacting second sidewalls of the channels (sidewalls of 20 in X direction); a gate spacer (55) on an upper sidewall of the gate structure (55 on upper sidewall of 108, 106); a nitrogen-containing portion (104 ¶ [0042], [0091]) at an upper portion of an uppermost one of the channels (formed above uppermost channel 20); and an oxide pattern (102) between an upper surface of each of opposite end portions of the uppermost one of the channels (opposite ends of upper surface of uppermost 20) and a lower surface of the gate spacer (lower surface of 55 ¶ [0091]).
However, the prior art fails to teach or reasonably suggest “wherein a portion of the gate structure is positioned along the upper surface and between the nitrogen-containing portion and the oxide pattern” together with all the limitations of claim 16 as claimed. Claims 17-20 are allowable insofar as they depend upon and require all the limitations of claim 16.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20190221483 A1 – discloses a transistor structure comprising sidewall spacers 440 including silicon oxynitride (¶ [0059]-[0060]).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
Prosecution Insights