DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 10, 13-14, 22, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20230307303 (Kishigui et al) further in view of CN 208588493 (Yazawa et al). For convenience a machine translation of Yazawa by Espacenet has been provided in this office action.
As to Claim 1, Kishigui teaches a semiconductor package (Kishigui Fig 2), comprising:
a semiconductor die including a device side having circuitry formed therein, the device side including a sensor (30 having detector assembly 40 on the top side thereof);
a metal member creating a hollow cavity extending through the metal member (60 defines hollow cavity), the hollow cavity vertically aligned with the sensor (opening aligned with 40), the metal member including a lower portion having a first thickness (61, first wall thickness measured along the horizontal direction in Fig 2) and an upper portion having varying thicknesses greater than and less than the first thickness (62, wherein the wall thicknesses are measured at a 45 degree angle between the horizontal and vertical axes in Fig 2), an intersection of the upper and lower portions forming a notch on an outer side of the metal member opposing the hollow cavity (notch formed at joining of 61/62); and
a mold compound covering portions of the semiconductor die and contacting the metal member (50+70).
Kishigui fails to explicitly teach wherein the mold compound is in direct contact with the upper portion. Rather, Kishigui only explicitly shows the mold compound being in direct contact with the lower portion (Kishigui Fig 2, mold compound 50+70 directly contacting lower portion 61).
Yazawa teaches a device similar to that of Kishigui, explicitly having a mold compound covering portions of a semiconductor die and in direct contact with an upper portion of a covering member (Yazawa Fig 8, mold compound 50 covering portions of 15 in direct contact with horizontal portion of cover 30).
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the semiconductor device taught by Kishigui with the mold compound being allowed to directly contact an upper portion taught by Yazawa. Allowance for the mold compound to directly contact the upper portion may simplify the manufacturing process for the device as opposed to the mold compound being required to directly contact only the lower portion.
As to Claim 2, The combination of Kishigui and Yazawa teaches the semiconductor package of claim 1, wherein the thicknesses of the upper portion decrease from a bottom of the upper portion to a top of the upper portion (measurement of thicknesses described in claim 1 rejection satisfy this limitation).
As to Claim 3, The combination of Kishigui and Yazawa teaches the semiconductor package of claim 1, wherein the hollow cavity has a uniform diameter (diameter in horizontal direction defined by 60 uniform).
As to Claim 4, The combination of Kishigui and Yazawa teaches the semiconductor package of claim 1, wherein the hollow cavity has a cylindrical shape (opening defined by 60 cylindrical; see Fig 1).
As to Claim 10, The combination of Kishigui and Yazawa teaches a semiconductor package (Fig 2), comprising:
a semiconductor die having a sensor (30 having sensor 40);
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a metal member having a hollow cavity extending through the metal member and vertically aligned with the sensor (cavity defined through 60 and aligned with 40), the metal member including a lower portion having a uniform thickness (61, thickness measured along horizontal direction in Fig 2) and an upper portion having opposing first and second ends (62, first/second ends labeled in specifically-labeled annotated Kishigui Fig 2), the first end closest to the lower portion and the second end farthest from the lower portion (see appropriate annotated Fig 2), a thickness of the upper portion tapering from the first end to the second end (first/second ends taper as claimed); and
a mold compound contacting an outer surface of the metal member and covering the semiconductor die (50+70 contacts surface 60A and covers 30).
Kishigui fails to explicitly teach wherein the mold compound is in direct contact with the upper portion. Rather, Kishigui only explicitly shows the mold compound being in direct contact with the lower portion (Kishigui Fig 2, mold compound 50+70 directly contacting lower portion 61).
Yazawa teaches a device similar to that of Kishigui, explicitly having a mold compound covering portions of a semiconductor die and in direct contact with an upper portion of a covering member (Yazawa Fig 8, mold compound 50 covering portions of 15 in direct contact with horizontal portion of cover 30).
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the semiconductor device taught by Kishigui with the mold compound being allowed to directly contact an upper portion taught by Yazawa. Allowance for the mold compound to directly contact the upper portion may simplify the manufacturing process for the device as opposed to the mold compound being required to directly contact only the lower portion.
As to Claim 13, The combination of Kishigui and Yazawa teaches the semiconductor package of claim 10, further comprising conductive terminals exposed to an exterior of the mold compound and coupled to a device side of the semiconductor die on which the sensor is positioned (20 includes external connections on surface 20C being electrically connected top side of 30 ¶0046).
As to Claim 14, The combination of Kishigui and Yazawa teaches the semiconductor package of claim 10, wherein a lower surface of the upper portion extends farther away from the hollow cavity than the lower portion extends away from the hollow cavity (indicated corner on appropriate annotated Fig 2 further away from cavity than portion 61A of 61 does), and wherein the lower surface of the upper portion mitigates risk of the mold compound separating from the metal member (notch prevents the O-ring OR from sliding, improving stability of device and thereby mitigating risk of mold compound separating from the metal member).
As to Claim 22, The combination of Kishigui and Yazawa teaches a semiconductor package (Fig 2), comprising:
a semiconductor die including a sensor on a device side of the semiconductor die, the sensor exposed to an ambient environment (30 having sensor 40 on top side, with 40 exposed through the openings);
a metal wall (60) having inner and outer surfaces, the inner surface surrounding and facing the sensor and the outer surface facing away from the sensor (61B/61A facing towards and away from the sensor, respectively), the metal wall having a lower portion with a uniform thickness (63 has uniform horizontal thickness) and an upper portion with varying thicknesses that increase from top to bottom (61+62 have thicknesses increasing in the direction from the top-outer corner of 62 towards the opening at an angle of 45 degrees below the horizontal); and
a mold compound contacting the outer surface and covering at least part of the semiconductor die (50+70).
Kishigui fails to explicitly teach wherein the mold compound is in direct contact with the upper portion. Rather, Kishigui only explicitly shows the mold compound being in direct contact with the lower portion (Kishigui Fig 2, mold compound 50+70 directly contacting lower portion 61).
Yazawa teaches a device similar to that of Kishigui, explicitly having a mold compound covering portions of a semiconductor die and in direct contact with an upper portion of a covering member (Yazawa Fig 8, mold compound 50 covering portions of 15 in direct contact with horizontal portion of cover 30).
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the semiconductor device taught by Kishigui with the mold compound being allowed to directly contact an upper portion taught by Yazawa. Allowance for the mold compound to directly contact the upper portion may simplify the manufacturing process for the device as opposed to the mold compound being required to directly contact only the lower portion.
As to Claim 24, the combination of Kishigui and Yazawa teaches the semiconductor package of claim 22. Kishigui further teaches wherein a bottom surface of the upper portion extends farther away from the inner surface than the lower portion extends away from the inner surface (indicated corner on appropriate annotated Fig 2 further away from cavity than portion 61A of 61 does), and wherein the bottom surface of the upper portion mitigates risk of the mold compound separating from the metal wall (notch prevents the O-ring OR from sliding, improving stability of device and thereby mitigating risk of mold compound separating from the metal wall).
Claim(s) 5, 11-12, 15, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kishigui and Yazawa as applied to claims 1, 10, and 22 above, and further in view of CN 210894101 (Tao et al). For convenience the examiner references a machine translation of Tao by Espacenet provided in this office action.
As to Claim 5, The combination of Kishigui and Yazawa teaches the semiconductor package of claim 1 but fails to explicitly teach wherein a diameter of the hollow cavity ranges from 100 microns to 150 microns.
Tao discloses a device which is similar to that of The combination of Kishigui and Yazawa, in that it describes a housing for a sensor similar to The combination of Kishigui and Yazawa. Specifically, Tao discloses the diameter for a gas sensing chamber being 100-2000 µm (Tao ¶0048).
It would have been obvious, in light of Tao teaching the scale of analogous sensors known to those in the art at the time of filing, that a diameter of the hollow cavity disclosed by The combination of Kishigui and Yazawa can range from 100 microns to 150 microns.
As to Claim 11, The combination of Kishigui and Yazawa teaches the semiconductor package of claim 10, but fails to explicitly teach wherein a diameter of the hollow cavity ranges from 100 microns to 150 microns.
Tao, for the same reasons as those applied to the claim 5 rejection above, renders obvious that a diameter of the hollow cavity disclosed by The combination of Kishigui and Yazawa can range from 100 microns to 150 microns.
As to Claim 12, the combination of Kishigui, Yazawa, and Tao teaches the semiconductor package of claim 11. Kishigui further teaches wherein the diameter of the hollow cavity does not vary along a length of the hollow cavity (diameter of 64 along 61 does not vary).
As to Claim 15, the combination of Kishigui and Yazawa teaches the semiconductor package of claim 10, but fails to explicitly teach wherein the thickness of the upper portion is at least 40 microns.
Tao, for the same reasons as those applied to the claim 5 rejection above, renders obvious that a horizontal thickness of the upper portion disclosed by Kishigui and Yazawa can be at least 40 microns.
As to Claim 25, the combination of Kishigui and Yazawa teaches the semiconductor package of claim 22, but fails to explicitly teach wherein the thicknesses of the upper portion are at least 40 microns.
Tao, for the same reasons as those applied to the claim 5 rejection above, renders obvious that the thickness of the upper portion disclosed by Kishigui and Yazawa can be at least 40 microns.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kishigui and Yazawa as applied to claim 22 above, and further in view of US 20090266173 (Kobayashi et al).
As to Claim 23, the combination of Kishigui and Yazawa teaches the semiconductor package of claim 22, but fails to explicitly teach conductive terminals exposed to an exterior of the mold compound and coupled to the device side of the semiconductor die. While examiner notes that they reasonably expect the device taught by Kishigui and Yazawa to have such terminals in order for the package to be connected to further devices, they do not explicitly disclose them.
Kobayashi teaches a semiconductor package similar to that of Kishigui and Yazawa, explicitly having conductive terminals exposed to an exterior of a mold compound (Kobayashi Figs. 1-2 terminals 6 exposed to exterior of molded portion 2 ¶0044) which are coupled to a device side of a semiconductor die (6 coupled to top side of pressure detecting element 4).
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the semiconductor package taught by Kishigui and Yazawa with the externally-exposed conductive terminals taught by Kobayashi in order to electrically access the die and sensor of Kishigui and Yazawa for connection to additional devices.
Response to Arguments
Applicant’s arguments filed 15 May 2026, with respect to the rejection(s) of claim(s) 1-4, 10, 13-14, and 22 under 35 USC §102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the combination of Kishigui and Yazawa presented above.
Examiner notes that all remaining pending claims also have new grounds of rejection due to their respective dependences upon claims rejected by the combination of Kishigui and Yazawa.
Examiner also notes applicant’s argument that the mold compound 50 of Kishigui is not in direct contact with elements 61 and 62 due to an intervening adhesive 70 (see applicant arguments pg. 8). This argument is considered persuasive, and as a result examiner has amended the rejection of claim 22 such that elements 50+70 are now collectively considered to be “a mold compound”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Corbyn D Mellinger whose telephone number is (703)756-5683. The examiner can normally be reached M-F 9-6 Eastern.
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/Corbyn D Mellinger/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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