DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on May 7th, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
Applicant's response filed on May 7th, 2026 is acknowledged and isanswered as follows.
Applicant's arguments, see pgs. 6- 8, with respect to the rejection of the claims 15, 18, 24-28, 30 and 34 under 35 U.S.C. § 103(a) have been fully considered but they are not persuasive in view of the following reasons.
Applicant argues that Deppisch does not require grinding and grinding is merely one option and there would be no assume roughness difference between surface (see Applicant’s argument and pg. 7). The Examiner respectfully disagrees because even though grinding is one of the options for creating the concavity 104, it is still a fact that grinding can be chosen as one of the choices for forming concavity 104 to results in roughness difference for meeting the claim language (see Deppisch and [0021]).
Applicant further argues that different roughness is not an inherent or inevitable result and a ground surface can be polished or finished to achieve the same roughness as an unground surface (see Applicant’s argument). The Examiner respectfully disagrees because there is no support teaching that the ground surface of concavity 104 will be polished or finished to achieve the same roughness as unground surface. Furthermore, it is a fact that when surface is grinded the roughness of the ground surface will be different from the unground surface and Deppisch does not need to teach the difference of roughness, but the process of grinding would cause the difference of roughness between two surfaces.
In view of the foregoing reasons, the examiner believes that all Applicant's arguments and remarks are addressed. The examiner has determined that the previous Office Action is still proper based on the above responses. Therefore, the rejections are maintained.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 15, 18, 24-28, 30, 34-35 and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Fig. 5 of Deppisch et al. (Pub. No.: US 2008/0017975 A1), hereinafter as Embodiment 5 of Deppisch in view of Fig. 1 of Deppisch et al. (Pub. No.: US 2008/0017975 A1), hereinafter as Embodiment 1.
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Regarding claim 15, Embodiment 5 of Deppisch discloses a semiconductor
assembly in Fig. 5 comprising: a substrate (substrate 535) (see [0031]); a die (semiconductor device 525 on the left) coupled to the substrate (see [0032]); a lid (integrated heat spreader IHS 545 being metal as same material as IHS 101) coupled to the substrate and enclosing the die (see Fig. 5 and [0017], [0031]), the lid including: a first area of exposed metal (an exposed area of the top surface of HIS 545) (see annotated Fig. 5 above); a second area of exposed metal (an exposed area of the inner sidewall of concavity 575) (see annotated Fig. 5 above and [0031]); and a pedestal (the protrusion of IHS 545 and portions of solder material 555 as shown by the box in annotated Fig. 5 above) with a surface (defined by the bottom surface of the protrusion of IHS 545 having portions of solder material 555 in the box as shown in annotated Fig. 5 above), the surface of the pedestal including an area of thermally conductive material (an area of solder material 555 contacting semiconductor device 525 in the box of annotated Fig. 5 above) and contacting a surface of the die (top surface of semiconductor device 525 on the left) (see [0031-0032]).
Embodiment 5 of Deppisch fails to disclose wherein the first area of exposed metal has a roughness different from the roughness of the second area of exposed metal.
Embodiment 1 of Deppisch discloses a semiconductor a lid (an IHS including body portion 101) including a first area of exposed metal (an exposed area of the top surface of body portion 101) and a second area of exposed metal (an exposed area of the inner sidewall of concavity 104) (see Fig. 1 and [0017], [0020]), wherein the first area of exposed metal (the top surface of body portion 101 not being grinded and has a first roughness) has a roughness different from the roughness of the second area of exposed metal (the concavity 104 formed by grinding and the exposed area of the inner sidewall of concavity 104 have a second roughness) (the second roughness is greater than the first roughness due to grinding process to form the concavity 104) (see [0020-0021]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the grinding method of forming the concavity 104 of Embodiment 1 of Deppisch into the method of forming the concavity 575 of Embodiment 5 as the result for making the first area of exposed metal has a roughness different from the roughness of the second area of exposed metal. This is because having the grinding method for forming the concavity of the lid would provide a conventional and reliable method of cutting with low manufacturing cost.
Regarding claim 18, the combination of Embodiment 1 and Embodiment 5 of Deppisch discloses the semiconductor assembly of claim 15, wherein: the area of the thermally conductive material of the surface of the pedestal is less than a total area of the surface of the pedestal (area of portions of solder material 555 does not cover the entire surface area of the protrusion of IHS 545 as shown by the box in annotated Fig. 5 above); and the first area of exposed metal is on the surface of the pedestal external to the area of the thermally conductive material (the exposed area of the top surface of IHS 545 is outside of the enclosure of IHS 545) (see annotated Fig. 5 above).
Regarding claim 24, the combination of Embodiment 1 and Embodiment 5 of Deppisch discloses the semiconductor assembly of claim 15, wherein the thermally conductive material comprises a plated metal layer (solder material 555 has same material as solder material 210 as indium formed by electroplating) disposed on the surface of the pedestal (see Deppisch, Figs. 2, 5 and [0025], [0031]).
Regarding claim 25, the combination of Embodiment 1 and Embodiment 5 of Deppisch discloses the semiconductor assembly of claim 24, wherein the plated metal layer extends over both a top surface and one or more side surfaces of the pedestal (solder material 555 over the bottom surfaces and side surfaces of the protrusion of IHS 545 in annotated Fig. 5 above).
Regarding claim 26, the combination of Embodiment 1 and Embodiment 5 of Deppisch discloses the semiconductor assembly of claim 15, wherein the surface of the pedestal includes a plurality of discrete plated portions (two discrete solder material 555) configured to contact a corresponding plurality of dies (contacting two semiconductor dies 525) (see Fig. 5 and [0031]).
Regarding claim 27, the combination of Embodiment 1 and Embodiment 5 of Deppisch discloses the semiconductor assembly of claim 15, wherein the lid is coupled to the substrate by an adhesive layer (IHS 545 attached to substrate 535 using an adhesive being unlabeled) (see Fig. 5 and [0017]).
Regarding claim 28, Embodiment 5 of Deppisch discloses a lid (integrated heat spreader IHS 545 being metal as same material as HIS 101) configured to couple to a substrate (substrate 535) and enclosed a die (semiconductor device 525 on the left) (see Fig. 5, [0017] and [0031-0031]), the lid including: a first area of exposed metal (an exposed area of the top surface of IHS 545) (see annotated Fig. 5 above); a second area of exposed metal (an exposed area of the inner sidewall of concavity 575) (see annotated Fig. 5 above and [0017], [0031]); and a pedestal (the protrusion of IHS 545 and portions of solder material 555 as shown by the box in annotated Fig. 5 above) with a surface (defined by the bottom surface of the protrusion of IHS 545 having portions of solder material 555 in the box as shown in annotated Fig. 5 above), the surface of the pedestal including an area of thermally conductive material (an area of solder material 555 contacting semiconductor device 525 in the box of annotated Fig. 5 above) and contacting a surface of the die (top surface of semiconductor device 525 on the left) (see [0031-0032]).
Embodiment 5 of Deppisch fails to disclose wherein the first area of exposed metal has a roughness different from the roughness of the second area of exposed metal.
Embodiment 1 of Deppisch discloses a semiconductor a lid (an IHS including body portion 101) including a first area of exposed metal (an exposed area of the top surface of body portion 101) and a second area of exposed metal (an exposed area of the inner sidewall of concavity 104) (see Fig. 1 and [0017], [0020]), wherein the first area of exposed metal (the top surface of body portion 101 not being grinded and has a first roughness) has a roughness different from the roughness of the second area of exposed metal (the concavity 104 formed by grinding and the exposed area of the inner sidewall of concavity 104 have a second roughness) (the second roughness is greater than the first roughness due to grinding process to form the concavity 104) (see [0020-0021]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the grinding method of forming the concavity 104 of Embodiment 1 of Deppisch into the method of forming the concavity 575 of Embodiment 5 as the result for making the first area of exposed metal has a roughness different from the roughness of the second area of exposed metal. This is because having the grinding method for forming the concavity of the lid would provide a conventional and reliable method of cutting with low manufacturing cost.
Regarding claim 30, the combination of Embodiment 1 and Embodiment 5 of Deppisch discloses the lid of claim 28, wherein: the area of the thermally conductive material of the surface of the pedestal is less than a total area of the surface of the pedestal (area of portions of solder material 555 does not cover the entire surface area of the protrusion of IHS 545 as shown by the box in annotated Fig. 5 above); and the first area of exposed metal is on the surface of the pedestal external to the area of the thermally conductive material (the exposed area of the top surface of IHS 545 is outside of the enclosure of IHS 545) (see annotated Fig. 5 above).
Regarding claim 34, the combination of Embodiment 1 and Embodiment 5 of Deppisch discloses the lid of claim 28, wherein the thermally conductive material comprises a plated metal layer (solder material 555 has same material as solder material 210 as indium formed by electroplating) disposed on the surface of the pedestal (see Deppisch, Figs. 2, 5 and [0025], [0031]).
Regarding claim 35, the combination of Embodiment 1 and Embodiment 5 of Deppisch discloses the semiconductor assembly of claim 15, but fails to disclose wherein the first area of exposed metal has a roughness (Ra) of 1.0 um or greater and the second area of exposed metal has a roughness (Ra) of less than 0.5 um.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the lid comprising wherein the first area of exposed metal has a roughness (Ra) of 1.0 um or greater and the second area of exposed metal has a roughness (Ra) of less than 0.5 um because the roughness value can be controlled by the process of manufacturing for meeting standard of having high performance device. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 38, the combination of Embodiment 1 and Embodiment 5 of Deppisch discloses the semiconductor assembly of claim 28, but fails to disclose wherein the first area of exposed metal has a roughness (Ra) of 1.0 um or greater and the second area of exposed metal has a roughness (Ra) of less than 0.5 um.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the lid comprising wherein the first area of exposed metal has a roughness (Ra) of 1.0 um or greater and the second area of exposed metal has a roughness (Ra) of less than 0.5 um because the roughness value can be controlled by the process of manufacturing for meeting standard of having high performance device. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Claims 17, 19-20 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Fig. 5 of Deppisch et al. (Pub. No.: US 2008/0017975 A1), hereinafter as Embodiment 5 of Deppisch in view of Fig. 1 of Deppisch et al. (Pub. No.: US 2008/0017975 A1), hereinafter as Embodiment 1, as applied to claims 15 and 28 above and further in view of Kelly et al. (Pub. No.: US 2014/0134804 A1), hereinafter as Kelly.
Regarding claim 17, the combination of Embodiment 5 and Embodiment 1 of Deppisch discloses the semiconductor assembly of claim 15, wherein the pedestal further sides (slanted sides of the protrusion of IHS 545 and portions of solder material 555) and at least one side comprises thermally conductive material (portions of solder material 555) (see annotated Fig. 5 above and [0031]). However, the combination of Embodiment 5 and Embodiment 1 of Deppisch fails to disclose the sides substantially perpendicular to the surface of the pedestal.
Kelly discloses a semiconductor assembly in Fig. 1A comprising: a substrate (substrate 103) (see [0023]); a die (one die 101) coupled to the substrate (coupled through interposer 107) (see [0025]); a lid (lid 113) coupled to the substrate and enclosing the die (see [0026]), the lid including a pedestal (the protrusion of lid 113 above dies 101 and thermal interface material 118) with a surface (the bottom surface of the protrusion of lid 113 having thermal interface material 118 formed thereon) and sides (sides of the protrusion of lid 113) substantially perpendicular to the surface of the pedestal (the sides of the protrusion is perpendicular to the bottom surface of the protrusion of the lid 113) (see Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the sides of the pedestal of Embodiment 5 of Deppisch to be perpendicular to the surface of the pedestal as same as the pedestal of Kelly because the dimension and shape of pedestal can be modified through manufacturing for meeting certain standard of the manufacturing desire and requirement.
Regarding claim 19, the combination of Embodiment 5 and Embodiment 1 of Deppisch discloses the semiconductor assembly of claim 15, but fails to disclose the semiconductor assembly further comprising: a chip capacitor coupled to the substrate and enclosed by the lid, the chip capacitor coupled to the die via one or more connections in the substrate.
Kelly discloses a semiconductor assembly in Fig. 1A comprising: a substrate (substrate 103) (see [0023]); a die (one die 101) coupled to the substrate (coupled through interposer 107) (see [0025]); a lid (lid 113) coupled to the substrate and enclosing the die (see [0026]); a chip capacitor (passive device 105 on the left) coupled to the substrate and enclosed by the lid (see [0026-0027]); an additional chip capacitor (passive device 105 on the right) coupled to the substrate and enclosed by the lid, and the chip capacitor and the additional capacitor coupled to the die via one or more connections (conductive trace) in the substrate (see [0026-0027]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the chip capacitor and the additional capacitor of Kelly into the semiconductor assembly of Embodiment 5 of Deppisch for coupling to the die via one or more connections in the substrate because the modified structure would provide more compact IC package and more functionality for semiconductor assembly with lower manufacturing.
Regarding claim 20, the combination of Embodiment 5, Embodiment 1 of Deppisch and Kelly discloses the semiconductor assembly of claim 19, further comprising: an additional chip capacitor (passive device 105 on the right) coupled to the substrate and enclosed by the lid, the additional chip capacitor coupled to the die via one or more connections (conductive trace) in the substrate (see Kelly, Fig. 1A and [0026-0027]).
Regarding claim 29, the combination of Embodiment 5 and Embodiment 1 of Deppisch discloses the semiconductor assembly of claim 28, wherein the pedestal further sides (slanted sides of the protrusion of IHS 545 and portions of solder material 555) and at least one side comprises thermally conductive material (portions of solder material 555) (see annotated Fig. 5 above and [0031]). However, the combination of Embodiment 5 and Embodiment 1 of Deppisch fails to disclose the sides substantially perpendicular to the surface of the pedestal.
Kelly discloses a semiconductor assembly in Fig. 1A comprising: a substrate (substrate 103) (see [0023]); a die (one die 101) coupled to the substrate (coupled through interposer 107) (see [0025]); a lid (lid 113) coupled to the substrate and enclosing the die (see [0026]), the lid including a pedestal (the protrusion of lid 113 above dies 101 and thermal interface material 118) with a surface (the bottom surface of the protrusion of lid 113 having thermal interface material 118 formed thereon) and sides (sides of the protrusion of lid 113) substantially perpendicular to the surface of the pedestal (the sides of the protrusion is perpendicular to the bottom surface of the protrusion of the lid 113) (see Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the sides of the pedestal of Embodiment 5 of Deppisch to be perpendicular to the surface of the pedestal as same as the pedestal of Kelly because the dimension and shape of pedestal can be modified through manufacturing for meeting certain standard of the manufacturing desire and requirement.
Claims 36 and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Fig. 5 of Deppisch et al. (Pub. No.: US 2008/0017975 A1), hereinafter as Embodiment 5 of Deppisch in view of Fig. 1 of Deppisch et al. (Pub. No.: US 2008/0017975 A1), hereinafter as Embodiment 1, as applied to claims 15 and 28 above and further in view of Chen et al. (Pub. No.: US 2020/0135613 A1), hereinafter as Chen.
Regarding claim 36, the combination of Embodiment 5 and Embodiment 1 of Deppisch discloses the semiconductor assembly of claim 15, fail to disclose the lid comprising wherein the first area of exposed metal and the second area of exposed metal comprise nickel or a nickel alloy.
Chen discloses a semiconductor assembly comprising a lid (lid 65) comprising a first area of exposed metal (one inner portion of lid 65) and a second area of exposed metal (another inner portion of lid 65) comprise nickel or a nickel alloy (see Fig. 7 and [0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the material of the lid of Chen into the semiconductor assembly of Deppisch for making the lid because the modified structure would provide well known material with low manufacturing cost for making the lid.
Regarding claim 38, the combination of Embodiment 5 and Embodiment 1 of Deppisch discloses the semiconductor assembly of claim 28, fail to disclose the lid comprising wherein the first area of exposed metal and the second area of exposed metal comprise nickel or a nickel alloy.
Chen discloses a semiconductor assembly comprising a lid (lid 65) comprising a first area of exposed metal (one inner portion of lid 65) and a second area of exposed metal (another inner portion of lid 65) comprise nickel or a nickel alloy (see Fig. 7 and [0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the material of the lid of Chen into the semiconductor assembly of Deppisch for making the lid because the modified structure would provide well known material with low manufacturing cost for making the lid.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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