DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Non-Final office action base don application 18/345,437 filed June 30, 2023. Claims 1-20 are currently pending and have been considered below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 & 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph because of the claim limitation of “the first bond pad is coupled to a first via in the second die and the first bond pad is offset from the first via by a first dimension, and the second bond pad is coupled to a second via in the third die and the second bond pad is offset from the second via by a second dimension different than the first dimension”. However it is unclear what applicant is defining as a first dimension and second dimension different from the first dimension. Applicant drawings such as figure 1b, shows offsets (192/194) of vias (118) from bond pads (117a) wherein the offsets are smaller or larger to varying amounts in a y-direction/y-axis. Therefore it is unclear if “different dimension” is defined as a particular amount of variation of an offset for a particular direction or if a “different dimension” is intended to mean the offset is additionally offset in another axis/dimension such as the x-axis/z-axis. Claim 2-11 are also rejected based on their dependency from claim 1.
Likewise claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph because of the claim limitation of “the first bond pad is further offset from the first via by a first dimension and the second bond pad is further offset from the second via in a second dimension different than the first dimension”. Similar to claim 1 above, it is unclear what applicant is defining as a first dimension and second dimension different from the first dimension. Applicant drawings such as figure 1b, shows offsets (192/194) of vias (118) from bond pads (117a) wherein the offsets are smaller or larger to varying amounts in a y-direction/y-axis. Therefore it is unclear if “different dimension” is defined as a particular amount of variation of an offset for a particular direction or if a “different dimension” is intended to mean the offset is additionally offset in another axis/dimension such as the x-axis/z-axis.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 8, 10-13, 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (Pre-Grant Publication 2022/0130801).
Regarding claim 1, Lee discloses a microelectronic assembly comprising:
a first die (Fig. 12, 50a/50b) in a first layer; and
a second die (40a) and a third die (40b) in a second layer, the second layer coupled to the first layer by hybrid bond (Paragraph [0036]) interconnects having a first bond pad (44a) and a second bond pad, wherein:
the first bond pad (44a) is coupled to a first via (43a) in the second die and the first bond pad is offset from the first via by a first dimension (Claim 3 & 4), and
the second bond pad (44b) is coupled to a second via (43b) in the third die and the second bond pad is offset from the second via by a second dimension different than the first dimension (Claim 3 & 4).
Regarding claim 2, Lee further discloses:
the first bond pad (44a) is further offset from the first via (43a) in a first direction/positive horizontal direction from a center of the first bond pad and the second bond pad (44b) is further offset from the second via (43b) in a second direction/negative horizontal direction from a center of the second bond pad different than the first direction (Claim 3 & 4).
Regarding claim 4, Lee further discloses:
the hybrid bond interconnects further include a third bond pad (54a), and the microelectronic assembly further comprising: a third via (53a) in the first die (50a) coupled to the third bond pad, wherein the third via is offset from the third bond pad by a third dimension different than the first dimension and the second dimension.
Regarding claim 8, Lee further discloses:
The first via (43a) is formed in a through via/cavity that extends through die (40a).
Regarding claim 10 & 11, Lee further discloses:
An interposer (30) electrically coupled to the first ide (50) via pads (32, 41,51) and vias (43) and a substrate (10) electrically coupled to the interposer.
Regarding claim 12, Lee discloses a microelectronic assembly comprising:
a first die (Fig. 12, 50a) in a first layer; and
a second die (40a) and a third die (40b) in a second layer, the second layer coupled to the first layer by interconnects including a first bond pad (44a) and a second bond pad (40b) in a dielectric material (45a/45b) wherein:
the first bond pad (44a) is coupled to a first via (43a) in the second die and the first bond pad is offset from the first via in a first direction/positive horizontal direction from a center of the first bond pad, and the second bond pad (44b) is coupled to a second via (43b) in the third die and the second bond pad is offset from the second via in a second direction/ negative horizontal direction from a center of the second bond pad different than the first direction (Claim 3 & 4).
Regarding claim 13, Lee further discloses:
the first bond pad (44a) is further offset from the first via (44b) by a first dimension and the second bond pad (44b) is further offset from the second via (44b) in a second dimension different than the first dimension (Claim 3 & 4).
Regarding claim 15, Lee further discloses:
The first via (43a) is formed in a through via/cavity that extends through die (40a).
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 16 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Elsherbini (Pre-Grant Publication 2024/0063089).
Regarding claim 16, Elsherbini discloses a micoelectronic assembly comprising:
a first die (Fig. 1a, 103) in a first layer; and
a second die (104) and a third die (105) in a second layer, wherein the second layer is coupled to the first layer by first interconnects (110) coupled to the second die 9104) having a first thickness and by second interconnects (110) coupled to the third die (105) having a second thickness different than the first thickness, wherein the first interconnects and the second interconnects have a pitch of sub-10 micrometers (Paragraph [0032]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (Pre-Grant Publication 2022/0130801) in view of Liff (Pre-Grant Publication 2022/0189850).
Regarding claims 5-7, Lee discloses all of the limitations of claim 1 (addressed above). Lee does not explicitly disclose an inorganic dielectric material or a liner around the second and third die. However Liff disclose an microelectronic assembly comprising:
An inorganic dielectric material (Fig. 1, 126; Paragraph [0025]) formed around multiple dies (102-1 & 102-2).
A liner (132) on and around the dies wherein the liner is between the inorganic material and the dies, and the liner has thickness between 10nm and 2 microns (Paragraph [0026]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the inorganic dielectric material and the liner around the dies because the inorganic material will serve to protect the dies and facilitate heat transfer of the dies (Paragraph [0025]). Further the liner around the dies may serve as an etch stop, hermetic seal, or a diffusion barrier to limit diffusion of metal atoms (Paragraph [0025]).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (Pre-Grant Publication 2022/0130801) in view of Park (Pre-Grant Publication 2022/0068829).
Regarding claim 9, Lee discloses all of the limitations of claim 1 (addressed above). Lee does not explicitly disclose an alignment mark. However Park discloses a semiconductor package comprising:
Hybrid bonding a first chip (Fig. 2, 100) to a second chip (200) wherein the chips include alignment key (134/234).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the alignment key in the chips because they will allow the chip to be precisely aligned in a desired position when bonded thereby improving product reliability (Paragraph [0059]).
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini (Pre-Grant Publication 2024/0063089) in view of Liff (Pre-Grant Publication 2022/0189850).
Regarding claims 17-19, Elsherbini discloses all of the limitations of claim 16 (addressed above). Elsherbini does not explicitly disclose an inorganic dielectric material or a liner around the second and third die. However Liff disclose an microelectronic assembly comprising:
An inorganic dielectric material (Fig. 1, 126; Paragraph [0025]) formed around multiple dies (102-1 & 102-2).
A liner (132) on and around the dies wherein the liner is between the inorganic material and the dies, and the liner has thickness between 10nm and 2 microns (Paragraph [0026]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the inorganic dielectric material and the liner around the dies because the inorganic material will serve to protect the dies and facilitate heat transfer of the dies (Paragraph [0025]). Further the liner around the dies may serve as an etch stop, hermetic seal, or a diffusion barrier to limit diffusion of metal atoms (Paragraph [0025]).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini (Pre-Grant Publication 2024/0063089) in view of Park (Pre-Grant Publication 2022/0068829).
Regarding claim 20, Elsherbini discloses all of the limitations of claim 1 (addressed above). Elsherbini does not explicitly disclose an alignment mark. However Park discloses a semiconductor package comprising:
Hybrid bonding a first chip (Fig. 2, 100) to a second chip (200) wherein the chips include alignment key (134/234).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the alignment key in the chips because they will allow the chip to be precisely aligned in a desired position when bonded thereby improving product reliability (Paragraph [0059]).
Allowable Subject Matter
Claim 14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 14 is considered allowable because none of the prior art either alone or in combination discloses the first bond pad has a first thickness, and wherein the interconnects further include a third bond pad having a second thickness different than the first thickness.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (Pre-Grant Publication 2025/0300135) disclose hybrid bonding a first and second element wherein pads are offset over through silicon via.
Krishnatreya (Pre-Grant Publication 2025/0006695) discloses a packaged structure including compensation layers for known-good-die to known-good-die hybrid bonding.
Chen (Pre-Grant Publication 2022/0262766) disclose a through dielectric via for direct connection/bonding.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM.
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/BRANDON C FOX/Examiner, Art Unit 2818
/DAVID VU/Primary Examiner, Art Unit 2818
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