DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US Pub. 2001/0033004; hereinafter “Lin”).
Regarding Claim 1, Lin discloses an electronic device, comprising: a semiconductor layer 17 (page 2, paragraph 35); a resistor (Rn) in the semiconductor layer 17 (page 2, paragraph 35; see fig. 3A); and a diode (Dn) in the semiconductor layer 17 (page 2, paragraph 35; see fig. 3A), wherein at least a portion of the resistor (Rn) includes or forms a p-n junction of the diode (Dn) (the resistor Rn comprises an n-type well region 18, and the diode Dn is disposed within the well region 18 and is formed by a PN junction formed between a p-type doped region 30 and the n-type well 18 (page 2, paragraph 35); therefore, the n-type well 18, which forms part of the resistor Rn, includes the PN junction of the diode Dn; see fig. 3A).
Regarding Claim 3, Lin discloses wherein: the resistor (Rn) includes a first terminal (20, 22) extended in a first well 18 in the semiconductor layer 17 (page 2, paragraph 35; see fig. 3A), the first well 18 including majority dopants of a first conductivity type (n-type; page 2, paragraph 35); and the p-n junction of the diode (Dn) is located in the first well 18 (page 2, paragraph 35; see fig. 3A).
Regarding Claim 4, Lin discloses wherein: the diode (Dn) includes a first region (a region of the n-type well 18 below the p-type doped region 30) and a second region 30 in the first well 18 (see fig. 3A), an interface between the first and second regions forming the p-n junction (page 2, paragraph 35; see fig. 3A), wherein the second region 30 extends from a surface (an upper surface) of the semiconductor layer 17 and abuts the first region (the region below the second region 30) disposed below the second region 30 (see fig. 3A); the first region (the region below the second region 30) includes majority dopants of the first conductivity type (n-type; page 2, paragraph 35; see fig. 3A); and the second region 30 includes majority dopants of a second conductivity type (p-type; page 2, paragraph 35; see fig. 3A) opposite the first conductivity type (n-type).
Regarding Claim 5, Lin discloses wherein the first terminal (20, 22) of the resistor (Rn) includes a third region (20, 22) in the first well 18 (see fig. 3A), the third region (20, 22) being spaced apart from the first and second regions (the first region is the region below the second region 30) (see fig. 3A) and including majority dopants of the first conductivity type (n-type; page 2, paragraph 35; see fig. 3A).
Allowable Subject Matter
Claims 2 and 6-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 recites the resistor and the diode are connected in parallel; the resistor conducts greater current than the diode when a voltage across the resistor is less than a threshold value; and the diode conducts greater current than the resistor when the voltage across the resistor is equal to or greater than the threshold value.
Claim 6 recites the resistor further includes: a second terminal extended in a second well in the semiconductor layer and spaced apart from the first terminal, the second well having majority dopants of the first conductivity type; and a doped region that extends between the first and second terminals, the doped region having majority dopants of the first conductivity type.
Claim 9 recites the diode includes a buried layer disposed below the first well and abutting the first well, an interface between the buried layer and the first well forming the p-n junction, wherein the buried layer includes majority dopants of a second conductivity type opposite the first conductivity type.
These features in combination with the other elements of the base claim are neither disclosed nor suggested by the prior art of record.
Claims 7, 8 and 10-14 variously depend from claims 6 or 9, so they are objected for the same reason.
Claims 15-24 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 15 recites a resistor having first and second terminals, the first terminal coupled to a drain of the p-channel MOSFET, and the second terminal coupled to a drain of the n-channel MOSFET; and a diode integrated with the resistor in a semiconductor layer and coupled in parallel.
Claim 20 recites forming a resistor in a semiconductor layer, including: forming a drift region including majority dopants of a first conductivity type in the semiconductor layer; forming first and second wells including majority carrier dopants of the first conductivity type in the semiconductor layer, the first and second wells extending to respective laterally opposite sides of the drift region; and forming first and second regions including majority dopants of the first conductivity type, the first region extending in the first well, and the second region extending in the second well.
These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 16-19 and 21-24 variously depend from claim 15 or 20, so they are allowed for the same reason.
Conclusion
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/CHEUNG LEE/Primary Examiner, Art Unit 2812 December 20, 2025