DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, including claims 1-17, in the reply filed on 12/1/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over Seddon et al. (Patent No. US 10,388,526 B1) in view of Du et al. (PG Pub. No. US 2022/0415750 A1).
Regarding claim 1, Seddon teaches a method for manufacturing a semiconductor die, comprising:
prior to forming circuitry on a semiconductor wafer, forming a horizontal array of cracks in an interior of the wafer using a laser (col. 4 lines 48-50 & col. 6 lines 26-28: horizontal array of cracks 16 formed in interior of substrate 2 with laser 12 before forming semiconductor devices); and
after forming the horizontal array of cracks, forming circuitry on a device side of the wafer (col. 4 lines 48-50, col 5 lines 14-17: processing of the substrate 2 to form semiconductor devices on device side 8 after forming cracks 16).
Seddon does not teach forming conductive bumps on the device side of the wafer.
Du teaches a method including forming conductive bumps (¶ 0023: 109) on a device side of a wafer (¶ 0023: 109 formed on device side 104 of wafer 102).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Seddon with conductive bump formation, as a means to physically and electrically couple the device side of the wafer to contact pads (¶ 0035, fig. 11), allowing for use as memory or logic die (Du, ¶ 0035).
Regarding claim 5, Seddon in view of Du teaches the method of claim 1, wherein forming the horizontal array of cracks comprises damaging the device side of the wafer by scattering of the laser (Seddon, figs. 5-7), and wherein forming the circuitry comprises forming circuitry on a damaged area of the wafer (Seddon, col. 4 lines 48-50 & col. 6 lines 26-28: horizontal array of cracks 16 formed in interior of substrate 2 with laser 12 before forming semiconductor devices).
Regarding claim 6, Seddon in view of Du teaches the method of claim 5, wherein the damage on the device side includes a melting of the wafer (Seddon, col. 5 lines 54-56).
Regarding claim 7, Seddon in view of Du teaches the method of claim 1, wherein a minimum distance between a crack in the horizontal array of cracks and the device side of the wafer is 30 microns (Seddon, col. 6 lines 18-19).
Regarding claim 8, Seddon in view of Du teaches the method of claim 1, wherein a distance between a crack in the horizontal array of cracks and the device side of the wafer is a function of an energy absorption rate of a material of which the wafer is composed (Seddon, col. 6 lines 11-16).
Regarding claim 9, Seddon in view of Du teaches the method of claim 1, wherein a power and a frequency of the laser is a function of an energy absorption rate of a material of which the wafer is composed (Seddon, col. 6 lines 11-16).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Seddon in view of Du as applied to claim 1 above, and further in view of Lin et al (PCT/CN 2021/097811, machine translation provided).
Regarding claim 2, Seddon in view of Du teaches the method of claim 1, including forming a horizontal array of cracks (Seddon, fig. 1).
Seddon in view of Du does not teach wherein forming the horizontal array of cracks includes forming a horizontal array of cracks that is vertically aligned with a saw street of the wafer.
Lin teaches a method including forming a horizontal array of cracks (¶ 0046 & fig. 9: 111) vertically aligned with a saw street of the wafer (¶ 0046, figs. 7-9: at least a portion of 111 formed by inner holes 102 vertically aligned with D1, D2 formed by surface holes 101; Examiner’s note: fig 8 appears to be mislabeled, as the written description defines element 101 as a surface hole, and 102 as an internal hole).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the horizontal array of cracks of Seddon in view of Lin with the saw street alignment of Lin, as a means to control the defects such as chipping.
Regarding claim 3, Seddon in view of Du and Lin teaches the method of claim 2, wherein the saw street has a width no wider than 10 microns (Lin, ¶ 0045: in at least one embodiment, surface hole 101 forming D1, D2 is 5um).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Seddon in view of Du as applied to claim 1 above, and further in view of Wyant et al. (US 2024/0332078 A1).
Regarding claim 10, Seddon in view of Du teaches the method of claim 1, further comprising backgrinding a non-device side of the wafer opposite the device side (Seddon, col. 1 lines 51-60)
Seddon in view of Du does not teach the method further comprising:
applying a tape to the device side of the wafer;
taping the non-device side of the wafer;
de-taping the device side of the wafer; and
expanding tape on the non-device side of the wafer to separate the wafer into individual, multiple semiconductor dies.
Wyant teaches a method including:
applying a tape to a device side of a wafer (¶ 0014 & fig. 1: step 102, backgrind tape applied to side 204 of wafer 200);
backgrinding a non-device side of the wafer opposite the device side (¶ 0015 & fig. 1: step 104);
taping the non-device side of the wafer (¶ 0023 & fig. 1: step 116, dicing tape applied to surface 202 of 200);
de-taping the device side of the wafer (¶ 0023 & fig. 1: step 118); and
expanding tape on the non-device side of the wafer to separate the wafer into individual, multiple semiconductor dies (¶ 0023 & fig. 1: step 120, dicing tape expanded to singulate die).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Seddon in view of Du with the additional steps of Wyant, as a means to facilitate packaging singulated die to produce a device according to virtually any packaging technology, including a wafer chip scale package, chip scale package or other package type (Wyant, ¶ 0024).
Regarding claim 11, Seddon in view of Du and Wyant teaches the method of claim 10, wherein backgrinding the non-device side of the wafer includes sufficiently grinding the non-device side to reveal the array of cracks in the wafer (Seddon, col. 11 lines 51-60: backgrinding wafer at least exposes and removes damage layers of figs. 1, 5-7).
Claims 12 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Wyant in view of Seddon and Kim et al. (PG Pub. No. US 2020/0075441 A1).
Regarding claim 12, Wyant teaches a method for manufacturing a semiconductor device, comprising:
receiving a semiconductor wafer (¶ 0014: 200) having cracks formed therein by a laser process (¶ 0020: 420 formed in 200 by laser 402), the laser process having damaged a device side of the wafer (¶ 0020 & fig. 4: crack damage 418 formed on device side 204 of wafer 200) and circuitry formed on the device side (¶ 0017: 409 formed on side 204) such that the laser process did not damage the circuitry (fig. 4: 418 not formed in region of 409);
applying a tape (¶ 0022: 600) to the device side of the wafer (fig. 6: 600 applied to side 204);
backgrinding a non-device side of the wafer opposite the device side (¶ 0022, fig. 7A: back side 202 ground while 600 affixed to side 204);
taping the non-device side of the wafer (¶ 0023: tape 800 applied to side 202);
de-taping the device side of the wafer (fig. 9: 600 removed from side 204);
expanding tape on the non-device side of the wafer to separate the wafer and to produce a semiconductor die (¶ 0023: 800 expanded to separate die); and
covering the semiconductor die with a mold compound to produce a semiconductor package (¶ 0024).
Wyant does not teach the semiconductor wafer having a horizontal array of cracks formed therein by a laser process, circuitry having been thereafter formed on the device side, or the method further comprises coupling the semiconductor die to a conductive terminal, and the conductive terminal exposed to an exterior of the semiconductor package.
Seddon teaches a semiconductor wafer having a horizontal array of cracks formed therein by a laser process (col. 4 lines 48-50 & col. 6 lines 26-28: horizontal array of cracks 16 formed in interior of substrate 2 with laser 12 before forming semiconductor devices), circuitry having been thereafter formed on the device side (col. 4 lines 48-50, col 5 lines 14-17: processing of the substrate 2 to form semiconductor devices on device side 8 after forming cracks 16).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor wafer of Wyant with a horizontal array of cracks, as a means to reduce the time required to thin the semiconductor substrate to a desired thickness (Seddon, col. 7 lines 3-4).
Wyant in view of Seddon does not teach the method further comprises coupling the semiconductor die to a conductive terminal, and the conductive terminal exposed to an exterior of the semiconductor package.
Kim teaches a method including coupling a singulated semiconductor die (¶ 0024: 208) to a conductive terminal (¶ 0024 & fig. 2A: 208 coupled to lads 214), and the conductive terminal exposed to an exterior of a molded semiconductor package (fig. 2A: 214 exposed from mold compound 220).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Wyant in view of Seddon with the exposed terminal of Kim, as a means to provide electrical connection to the die while protecting the die from environmental effects such as moisture.
Regarding claim 15, Wyant in view of Seddon and Kim teaches the method of claim 12, wherein backgrinding the non-device side comprises backgrinding until the horizontal array of cracks is exposed (Seddon, col. 11 lines 51-60: backgrinding wafer at least exposes and removes damage layers of figs. 1, 5-7).
Regarding claim 16, Wyant in view of Seddon and Kim teaches the method of claim 12, wherein the damage on the device side includes melting of the wafer (Seddon, col. 5 lines 54-56).
Regarding claim 17, Wyant in view of Seddon and Kim teaches the method of claim 12, wherein a minimum distance between a crack in the horizontal array of cracks and the device side of the wafer is 30 microns (Seddon, col. 6 lines 18-19).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Wyant in view of Seddon and Kim as applied to claim 12 above, and further in view of Lin.
Regarding claim 13, Wyant in view of Seddon and Kim teaches the method of claim 12, comprising a saw street (Wyant, ¶ 0014: 208).
Wyant in view of Seddon and Kim does not teach wherein a saw street of the received wafer is 10 microns or less in width.
Lin teaches a wafer with a saw street 10 microns or less in width (¶ 0045: in at least one embodiment, surface hole 101 forming D1, D2 is 5um).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the saw street of Wyant in view of Seddon and Kim with a width less than 10 um, as a means to minimize waste and maximize active die size and corresponding manufacturing efficiency.
Allowable Subject Matter
Claims 4 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations stating:
“when the laser is applied to the second location, the laser scatters off of a contour of the second segment and extends to the device side of the wafer” as recited in claim 4, or
“the damage on the device side is formed by laser scatter off of a crack in the array of cracks” as recited in claim 14.
Conclusion
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/BRIAN TURNER/Examiner, Art Unit 2818