DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/30/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Invention I (Claims 1-16) in the reply filed on 12/22/2025 is acknowledged.
A. Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/22/2025.
Claim Status
Claims 1-16 are currently pending and being examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6, 9; and 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over BAEK et al (US 2023/0335559 A1, hereafter Baek) in view of Shao et al (US 2019/0318989 A1, hereafter Shao).
Re claim 1, Baek discloses in FIGS. 12 (with references to FIGS. 10A-10C) a semiconductor structure (300B) comprising:
a device layer (ACT1/ACT2/FP1/FP2; [0097]; [0124]; and [0126]);
a back end-of-line layer (195/M1; [0097] and [0124]); and
a backside power distribution layer (power lines ML1(PL1)/ML1’(PL2) and through conductive structures VS; [0128]-[0129] and claim 10) and including a first line network (through conductive structures VS) with having a first pitch (second pitch of claim 10; see P1 in inserted figure below), and a second line network (power lines ML1(PL1)/ML1’(PL2)) having a second pitch (first pitch of claim 10; see P2 in inserted figure below), wherein the second pitch (P2) is different than (claim 10) the first pitch (P2).
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For the record, the inserted figure (annotated FIG. 12 of Baek) depicts the first pitch (P1) of the first line network (VS) and the second pitch (P2) of the (ML1(PL1)/ML1’(PL2)).
Baek fails to disclose wherein the second pitch (P2) is greater than the first pitch (P1).
However,
Shao discloses in FIG. 1 a semiconductor structure metallization comprising: a first line network (110; [0031] and [0033]) having a first pitch (P1; [0033]) and a second line network (120; [0031] and [0033]) having a second pitch (P2; [0033]), where the first pitch (P1) can be the same distance (from 30-100 nm; [0033]) as the second pitch (P2), or a different distance (from 30-100 nm; [0033]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the backside power distribution layer of Baek, wherein the second pitch (P2) of the second line network is greater than the first pitch (P1) of the first line network, as disclosed by Shao, allowing an increased density of devices in the device layer since the separation (pitch) between devices could be decreased (i.e. a smaller P1).
Re claim 2, Baek and Shao disclose the semiconductor structure of claim 1.
But, do not explicitly disclose wherein the second pitch (P2) is at least 7 times (7x) greater than the first pitch (P1).
However, Shao discloses that pitches P1 and P2 are can be ranges from 30-100 nm ([0033]), with other ranges contemplated, determined by resolution constraint ([0033]). Thus, it would have been obvious through routine experimentation (MPEP § 2144.05) and the resolution constraints of the first metal line and second metal line, to have the first line and second line networks wherein the second pitch (P2) is at least 7 times (7x) greater than the first pitch (P1), allowing the increased density of devices in the device layer discussed for claim 1 in two directions since the separation (pitch) between devices could be decreased (i.e. a smaller P1).
Re claim 3, Baek discloses the semiconductor structure of claim 1.
But, fails to disclose wherein the first pitch (P1) is less than 180 nm.
However, Shao renders this limitation obvious by disclosing the first pitch (P1) ranges from 30-100 nm ([0033]), as would be part of the increased density of devices discussed for claim 1.
Re claim 4, Baek discloses the semiconductor structure of claim 1, wherein the first line network (through conductive structures VS) and the second line network (power lines ML1(PL1)/ML1’(PL2)) are connected (electrically to contact structures CAL; [0128]) by aligned vias (BP; [0128]).
Re claim 5, Baek discloses the semiconductor structure of claim 1, wherein the first line network (through conductive structures VS) includes a first portion (of ACT1) of first conductive lines (255; [0129]) to first conductivity type devices (P-type transistors; [0007]; [0090] and [0124]) in the device layer (ACT1/ACT2/FP1/FP2) and a second portion (of ACT2) of the first conductive lines (255) to second conductivity type devices (N-type transistors; [0007]; [0090] and [0124]), and wherein the second line network (power lines ML1(PL1)/ML1’(PL2)) includes a first portion (of ACT1) of conductive metal lines (ML1’) that is in direct contact with (physically touching) first portion (of ACT1) of conductive lines (255) from the first line network (through conductive structures VS) and the second line network (power lines ML1(PL1)/ML1’(PL2)) includes a second portion (of ACT2) of second conductive lines (ML1) in direct contact with (physically touching) the second portion (of ACT2) of conductive lines (255) from the first line network (through conductive structures VS).
Baek fails to disclose the first line network (through conductive structures VS) includes a first portion of first metal lines, and a second portion of the first metal lines; and the second line network (power lines ML1(PL1)/ML1’(PL2)) includes a second portion of second metal lines.
However, Shao discloses metals ([0035]) for the first line network (110) and the second line network (120) that could be used as part of the increased density of devices discussed for claim 1, the choice of metal(s) depending on the desired electrical and mechanical characteristics.
Re claim 6, Baek and Shao disclose the semiconductor structure of claim 5, wherein the first portion (of ACT1) of the first metal lines (255) in the first line network (VS) is isolated from the second portion (of ACT2) of second metal lines (ML1) in the second line network (ML1/ML1’) by a first dielectric cap (114), and the second portion (of ACT2) of the first metal lines (255) in the first line network (VS) is isolated from the first portion (ACT1) of the second metal lines (ML1) in the second line network (ML1/ML1’) by a second dielectric cap (251).
But, fail to disclose wherein the first dielectric cap (114) has a different composition than the second dielectric cap (251).
However, Baek discloses that the first dielectric cap (114) can include an oxide, a nitride, or a combination thereof ([0104]).
Thus, it would have been obvious to use a material of the second dielectric cap (251) different from the material of the first dielectric cap (114), since the choice (MPEP § 2144.04) of the material(s) for the second dielectric cap (251) has the consideration of preventing metal diffusion of the first metal lines (255) into the device layer.
Re claim 9, Baek discloses the semiconductor structure of claim 1.
But, fails to disclose the semiconductor structure further comprising a line width and pitch ratio of 5X to 10X.
However, Shao would render this limitation obvious by its disclose of first and second metal line widths of 15-40 nm ([0034]) which result in a line width and pitch ratio of 5X to 10X (~6.67 when pitch (P2) is 100 nm and metal layer (120) is 15 nm), which could be used as part of the increased density of devices discussed for claim 1.
Re claim 12, Baek discloses in FIG. 12 (with references to FIGS. 10A-10C) a semiconductor structure (300B) comprising:
a device layer (ACT1/ACT2/FP1/FP2; [0097]; [0124]; and [0126]) including first conductivity type devices (P-type transistors; [0007]; [0090] and [0124]), and second conductivity type devices (N-type transistors; [0007]; [0090] and [0124]), the first and second conductivity type devices (P-type/N-type transistors) having backside contacts (BP; [0125]);
a back end-of-line layer (195/M1; [0097] and [0124]);
a first line network (through conductive structures VS) of a backside power distribution level (power lines ML1(PL1)/ML1’(PL2) and through conductive structures VS; [0128]-[0129] and claim 10) having a first pitch (second pitch of claim 10; see P1 in inserted figure above) between adjacent first conductive lines (left/center/right through conductive structures VS), the first line network (through conductive structures VS) including a first portion (of ACT1) of via contacts (255; [0129]) to the first conductivity type devices (P-type transistors) and a second portion (of ACT2) of via contacts (255) to the second conductivity type devices (N-type transistors); and
a second line network (power lines ML1(PL1)/ML1’(PL2)) of the backside power distribution level (power lines ML1(PL1)/ML1’(PL2) and through conductive structures VS) having a second pitch (first pitch of claim 10; see P2 in inserted figure above) between adjacent second conductive lines (left ML1/PL1/center ML1’/PL2/right ML1/PL1), the second pitch (P2) being different than (claim 10) the first pitch (P1), wherein a first portion (of ACT1) of the second conductive lines (ML1’) connect the first portion (of ACT2) of via contacts (255) to the first conductivity type devices (P-type transistors) to a positive power supply (VDD; [0093]) and a second portion (of ACT2) of the second conductive lines (ML1) connect the second portion (of ACT2) of via contacts (255) to the second conductivity type devices (N-type transistors) to a negative power supply (VSS; [0093]).
Baek fails to disclose adjacent first metal lines, adjacent second metal lines, and the second pitch (P2) being greater than the first pitch (P1).
However,
Shao discloses in FIG. 1 a semiconductor structure metallization comprising: a first metal line network (110; [0031] and [0033]) having a first pitch (P1; [0033]) and a second metal line network (120; [0031] and [0033]) having a second pitch (P2; [0033]), where the first pitch (P1) can be the same distance (from 30-100 nm; [0033]) as the second pitch (P2), or a different distance (from 30-100 nm; [0033]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the backside power distribution layer of Baek, using the metal lines of Shao, wherein the second pitch (P2) of the second line network is greater than the first pitch (P1) of the first line network, as disclosed by Shao, producing adjacent first metal lines and adjacent second metal lines, allowing an increased density of devices in the device layer since the separation (pitch) between devices could be decreased (i.e. a smaller P1).
Re claim 13, Baek and Shao disclose the semiconductor structure of claim 12, wherein the second pitch is at least 7 times (7x) greater than the first pitch (see claim 2).
Re claim 14, Baek discloses the semiconductor structure of claim 12.
But, fails to disclose wherein the first line network (through conductive structures VS) and the second line network (power lines ML1(PL1)/ML1’(PL2)) are connected by aligned vias.
However, Shao discloses in the embodiment of FIG. 2 wherein the first line network (110) and the second line network (120) are connected by aligned vias (130; [0037] and [0046]).
Thus, it would have been obvious to further modify the structure of Baek by using the aligned vias of Shao to form merged conductive paths to different areas of the semiconductor structure (Shao; [0047]).
Re claim 15, Baek discloses the semiconductor structure of claim 12, wherein the first portion (of ACT1) of the via contacts (255) are to source and drain regions (120; [0097] and [0124]) of the first conductivity type devices (P-type transistors), and the second portion (of ACT2) of the via contacts (120) are to source and drain regions (120; [0097] and [0124]) of the second conductivity type devices (N-type transistors).
Re claim 16, Baek discloses the semiconductor structure of claim 12, wherein the second line network (power lines ML1(PL1)/ML1’(PL2)) further comprises a signal line (VDD or VSS; [0093]) in the backside power distribution level (power lines ML1(PL1)/ML1’(PL2) and through conductive structures VS).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Baek and Shao as applied to claim 1 above, and further in view of Noguchi et al (US 2001/0030367 A1, hereafter Noguchi).
Re claim 7, Baek and Shao disclose the semiconductor structure of claim 1.
But, fail to disclose wherein metal lines (of Shao) in the first line network (of Baek) have a liner present only at the base of the metal lines; and wherein metal lines in the second line network have a liner present on sidewalls and base surfaces of the metal lines.
However,
Noguchi discloses in FIG. 14 a semiconductor structure comprising wherein metal lines (37; [0183]-[0184) in a first line network (of interconnect plugs; [0183]) have a liner (TiN 45; [0208]) present only at the base (top) of the metal lines (37); and wherein metal lines (46a-46e; [0208]) in the second line network (of interconnections; [0208]) have a liner (TiN 45; [0208]) present on sidewalls (left/right vertical planes) and base surfaces (lower horizontal planes) of the metal lines (46a-46e).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Baek and Shao by adding the liner of Noguchi, such that metal lines in the first line network have a liner present only at the base of the metal lines; and metal lines in the second line network have the liner present on sidewalls and base surfaces of the metal lines, improving adhesion and diffusion properties between the first, the second metal lines, and surrounding dielectric caps (Noguchi; [0190]).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Baek and Shao as applied to claim 1 above, and further in view of Huang et al (US 2022/0044717 A1, hereafter Huang).
Re claims10-11, Baek and Shao disclose the semiconductor structure of claim 1,
But, fail to disclose the semiconductor structure further comprising a via bar length to width ratio of 5X to 10X; and further comprising a line resistance ratio of 20X to 50X.
However,
A. Shao discloses a line width and pitch ratio of 5X to 10X (see claim 9).
And,
B. Huang discloses in FIGS. 3M and 3M-1 a semiconductor structure (200) comprising a first metal line (260B; [0048]) length (L2; [0048]) of 5-500 nm ([0048]), a second metal line (260A; [0048]) width (W1; [0048]) of 20-100 nm, and a second metal line (260A; [0048]) length (L1; [0048]) of 100-10,000 nm ([0048]).
Thus, it would have been obvious through routine experimentation (MPEP § 2144.05) to use the line width and pitch ratio of Shao and the metal line lines’ lengths and widths of Huang with the first line network and the second line network of Baek, such that the semiconductor structure further comprises a via bar length to width ratio of 5X to 10X; and further comprises a line resistance ratio of 20X to 50X by having a substantially identical structure and composition (MPEP § 2112.01), reducing series resistance in the device layer (Huang; [0048]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
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/ERIC W JONES/Primary Examiner, Art Unit 2892