DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 3 in the reply filed on 6/26/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 and 17-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Re claim 1, line 9, the phrase “…so as to be…” is unclear and indefinite (i.e., it does not positive recite the device structure since the phrase generally refers to something that is in the future or yet/never to occur).
Re claim 1, lines 14-15, the phrase “the first electrical-modulation region and the second electrical- modulation region” lacks antecedent basis.
Re claim 1, lines 15-16, the phrase “…and to be arranged…” is unclear and indefinite (i.e., it does not positive recite the device structure since the phrase generally refers to something that is in the future or yet/never to occur).
Re claim 2, line 2, the phrase “the first elementary cell” lacks antecedent basis (i.e., same as the at least one first elementary cell or different?).
Re claim 2, line 5, the phrase “the first type” lacks antecedent basis.
Re claim 3, line 21-22, the phrase “the first elementary cell” lacks antecedent basis.
Re claim 3, line 24, the phrase “the second elementary cell” lacks antecedent basis.
Re claim 4, line 2, the phrase “the first elementary cell” lacks antecedent basis.
Re claim 4, lines 2-3, 7, 8, 9, 10-11, 12, 13-14; the phrase “the second elementary cell” lacks antecedent basis.
Re claim 5, lines 2, 4, 6, 8 and 10, the phrase “the first electrical-modulation region” lacks antecedent basis.
Re claim 5, lines 2, 4, 6-7, 8-9, 10-11, the phrase “the second electrical- modulation region” lacks antecedent basis.
Re claim 5, line 10, the phrase “the structure parameters i-iii” lacks antecedent basis.
Re claim 6, the phrase “the first electrical-modulation region” lacks antecedent basis.
Re claim 6, the phrase “the second electrical- modulation region” lacks antecedent basis.
Re claim 7, the phrase “the first electrical-modulation region” lacks antecedent basis.
Re claim 7, the phrase “the second electrical- modulation region” lacks antecedent basis.
Re claim 8, lines 2, 4, 6, the phrase “the third electrical-modulation region” lacks antecedent basis.
Re claim 8, the phrase “between the respective electrical-modulation regions of each pair of electrical- modulation regions adjacent to one another” is unclear and indefinite (e.g., between which electrical-modulation regions and/or which pair?).
Re claim 8, the phrase “the first, second, and third electrical-modulation regions” lacks antecedent basis.
Re claim 9, the phrase “the first, second, and third electrical-modulation regions” lacks antecedent basis.
Re claim 10, the phrase “the first electrical-modulation region” lacks antecedent basis.
Re claim 10, the phrase “the second electrical- modulation region” lacks antecedent basis.
Re claim 17, the phrase “A power MOSFET device, comprising: a semiconductor body including: a first main surface: and an active region extending from the first main surface into the semiconductor body; a gate dielectric layer on the first main surface in contact with the active region” is unclear and indefinite.
Re claim 18, line 4, the phrase “the body region” lacks antecedent basis.
Re claim 21, lines 6-7, the phrase “…so as to be…” is unclear and indefinite (i.e., it does not positive recite the device structure since the phrase generally refers to something that is in the future or yet/never to occur).
Re claim 21, lines 10 and 13, the phrase “the gate structure” lacks antecedent basis.
Re claim 21, lines 15 and 19, the phrase “the first electrical-modulation region” lacks antecedent basis.
Re claim 21, lines 15 and 19, the phrase “the second electrical- modulation region” lacks antecedent basis.
Re claim 23, the phrase “the first type” lacks antecedent basis.
Re claim 25, the phrase “The manufacturing process…” lacks antecedent basis.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ferruccio et al., EP1659636A1 from IDS.
Re claim 1, Ferruccio et al. disclose a power MOSFET device, comprising: a semiconductor body 4 (e.g, fig. 11) including: a first main surface (e.g., fig. 11); a second main surface opposite to the first main surface along a first axis (e.g., fig. 11); and an active area facing the first main surface (e.g., fig. 11); and an isolated-gate structure 7/8/10 (fig. 11) extending over the active area and including: a gate-oxide layer 7 of an insulating material extending over the first main surface (fig. 11); and a gate region 8 buried in the gate-oxide layer so as to be electrically insulated from the semiconductor body (fig. 11), the gate region including a gate layer 8 (fig. 11) of polysilicon and at least one first silicide electrical-modulation region 10 and one second silicide electrical-modulation region 10, the gate layer 8 having a top surface and a bottom surface opposite to one another along the first axis (fig. 11), the bottom surface of the gate layer 8 facing the main surface of the semiconductor body through the gate-oxide layer 7 (fig. 11), the first electrical-modulation region 10 and the second electrical- modulation region 10 extending in the gate layer so as to face the top surface of the gate layer and to be arranged alongside one another and spaced apart in a first plane orthogonal to the first axis (fig. 11), see pages 1-22 for more details.
Re claim 17. Ferruccio et al. disclose power MOSFET device, comprising: a semiconductor body 4 (e.g., fig. 11) including: a first main surface (e.g. fig. 11): and an active region extending from the first main surface into the semiconductor body (fig. 11); a gate dielectric layer 7 on the first main surface in contact with the active region (fig. 11); a gate electrode 8 (fig. 11) buried in the gate dielectric layer and including: a gate layer 8 (fig. 11) having: a first surface facing the active area (fig. 11); and a second surface opposite the first surface (fig. 11); a first silicide electrical modulation region 10 (fig. 11) extending from the second surface into the gate layer; and a second silicide electrical modulation region 10 (fig. 11) spaced apart from the first silicide electrical modulation region and extending from the second surface into the gate layer, see pages 1-22 for more details..
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK CHEN whose telephone number is (571)272-1689. The examiner can normally be reached Monday to Friday, 8am to 4pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JACK S CHEN/Primary Examiner, Art Unit 2893
Prosecution Insights