DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 30 Jun 2023 for application number 18/345,790. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and Claims.
Claims 1-30 are presented for examination. Elected claims 1-3, 7-11, and 27-30 are examined below. Non-elected claims 4-6 and 12-26 have been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07 Sep 2023 and 25 Feb 2025 were filed before the mailing of this Office Action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of claims 1-3, 7-11, and 27-30, drawn to Method Embodiment II. in the reply filed on 10 Mar 2026 is acknowledged.
Claims 4-6 and 12-23 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected embodiments, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10 Mar 2026.
Further, claims 24-26 are withdrawn, as these claims are drawn to a different embodiment (i.e. Fig. 15, for example) than the elected embodiment of Fig. 7.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. [hereinafter as Kim] (“Principle of direct van der Waals epitaxy of single-crystalline films on epitaxial graphene”, Nature Communications | 5:4836, 2014).
In reference to claim 1, Kim teaches A method of fabricating a compound semiconductor thin film structure, comprising:
epitaxially forming compound semiconductor epilayers [epitaxial growth of GaN; Figure 1(b), page 2, paragraph 0004] over a 2D material interlayer [graphene; Fig. 1(b), page 2, paragraph 0004] on a growth substrate [SiC substrate; Fig. 1(a), page 2, paragraph 0004];
lifting off the epilayers from the 2D material interlayer [release of GaN from the graphene layer/substrate; Fig. 1(d), page 2, paragraph 0004];
directly bonding a host substrate to the bottom surface of the compound semiconductor epilayers [host substrate bonded to bottom of GaN layer; Fig. 1(e), page 2, paragraph 0004]; and
exposing the top surface of the compound semiconductor epilayers to provide a thin film structure [top layer of GaN exposed, leaving a GaN film; Fig. 1(f), page 2, paragraph 0004].
In reference to claim 2, Kim teaches A method of fabricating a Ga-face thin film structure including a III-nitride (GaN) membrane, comprising:
epitaxially forming III-nitride GaN epilayers [epitaxial growth of GaN; Figure 1(b), page 2, paragraph 0004] over a 2D material interlayer [graphene; Fig. 1(b), page 2, paragraph 0004] on a growth substrate [SiC substrate; Fig. 1(a), page 2, paragraph 0004];
lifting off the GaN epilayers from the 2D material interlayer [release of GaN from the graphene layer/substrate; Fig. 1(d), page 2, paragraph 0004];
directly bonding a host substrate to the bottom surface of the GaN epilayers [host substrate bonded to bottom of GaN layer; Fig. 1(e), page 2, paragraph 0004]; and
exposing the top surface of the GaN epilayers to provide a Ga-face thin film structure [top layer of GaN exposed, leaving a GaN film; Fig. 1(f), page 2, paragraph 0004].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3, 7-10, and 27-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lee et al. [hereinafter as Lee] (US 2020/0135962 A1).
In reference to claim 3, Kim teaches the invention of claim 2.
However, Kim does not explicitly teach The fabrication method of claim 2 further comprising:
prior to lifting off the epilayers, directly wafer bonding a top host substrate to the top surface of the GaN epilayer; and
exposing the top surface of the GaN epilayers includes removing the top host substrate.
Lee teaches prior to lifting off the epilayers, directly wafer bonding a top host substrate to the top surface of the GaN epilayer [Fig. 2A, para 0032 discloses host substrate 276 attached to top surface of PV layer 274]; and
exposing the top surface of the GaN epilayers includes removing the top host substrate [para 0032 discloses removing host substrate 276, thereby exposing 274].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Kim and Lee before the effective filing date of the claimed invention, to include the host substrate as disclosed by Lee into the method of Kim in order to obtain method of manufacturing a semiconductor device which includes attaching a host substrate to the bottom and top of a GaN layer.
One of ordinary skill in the art would be motivated to obtain method of manufacturing a semiconductor device which includes attaching a host substrate to the bottom and top of a GaN layer to provide the predictable result of providing mechanical stabilization and also cutting costs by providing a reusable platform.
In reference to claim 7, Kim teaches A method of fabricating a GaN membrane thin film structure using direct wafer bonding, comprising:
epitaxially forming GaN epilayers [epitaxial growth of GaN; Figure 1(b), page 2, paragraph 0004] over a 2D material interlayer [graphene; Fig. 1(b), page 2, paragraph 0004] on a growth substrate [SiC substrate; Fig. 1(a), page 2, paragraph 0004];
directly bonding a second host substrate to the bottom of the epilayers [host substrate bonded to bottom of GaN layer; Fig. 1(e), page 2, paragraph 0004].
However, Kim does not explicitly teach directly wafer bonding a first host substrate to the top surface of the GaN epilayer ;
lifting off the GaN epilayers and the first host substrate from the 2D material interlayer to expose the bottom surface of the GaN epilayers;
removing the first host substrate from GaN epilayers to expose the top surface of the GaN epilayers and thereby provide a Ga-face thin film structure including the GaN epilayers and the second host substrate.
Kim and Lee teach directly wafer bonding a first host substrate to the top surface of the GaN epilayer [Lee, Fig. 2A, para 0032 discloses host substrate 276 attached to top surface of PV layer 274];
lifting off the GaN epilayers [release of GaN from the graphene layer/substrate; Fig. 1(d), page 2, paragraph 0004 of Kim] and the first host substrate [276 of Lee] from the 2D material interlayer [graphene; Fig. 1(b), page 2, paragraph 0004 of Kim] to expose the bottom surface of the GaN epilayers [GaN layer, of Kim];
removing the first host substrate from GaN epilayers to expose the top surface of the GaN epilayers [Lee, para 0032 discloses removing host substrate 276, thereby exposing 274] and thereby provide a Ga-face thin film structure including the GaN epilayers [GaN layer, of Kim] and the second host substrate [host substrate bonded to bottom of GaN layer; Fig. 1(e), page 2, paragraph 0004 of Kim].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Kim and Lee before the effective filing date of the claimed invention, to include the host substrate as disclosed by Lee into the method of Kim in order to obtain method of manufacturing a semiconductor device which includes attaching a host substrate to the bottom and top of a GaN layer.
One of ordinary skill in the art would be motivated to obtain method of manufacturing a semiconductor device which includes attaching a host substrate to the bottom and top of a GaN layer to provide the predictable result of providing mechanical stabilization and also cutting costs by providing a reusable platform.
In reference to claim 8, Kim and Lee teach the invention of claim 7.
Kim and Lee do not explicitly teach The fabrication method of claim 7 wherein directly wafer bonding the first host substrate to the GaN epilayer is performed in a wafer bonder.
However, it would have been obvious of one of ordinary skill in the art to use a wafer bonder to bond a host substrate to an epilayer, as using a wafer bonder was well-known in the art to perform such a function.
In reference to claim 9, Kim and Lee teach the invention of claim 7.
Kim teaches The fabrication method of claim 7 wherein lifting off the GaN epilayers includes applying mechanical shear force [release of GaN from the graphene layer/substrate; Fig. 1(d), page 2, paragraph 0004; page 4, paragraph 0001].
In reference to claim 10, Kim and Lee teach the invention of claim 7.
Kim teaches The fabrication method of claim 7 wherein lifting off includes mechanically guiding the fracture front across the weak van der Waals interactions dominating the surface of 2D material interlayers [release of GaN from the graphene layer/substrate; Fig. 1(d), page 2, paragraph 0004; page 4, paragraph 0001 discloses lifting, reaching van der Waals bonding energy stress].
In reference to claim 27, Kim teaches A method of fabricating a GaN membrane, comprising:
epitaxially forming GaN epilayers [epitaxial growth of GaN; Figure 1(b), page 2, paragraph 0004] over a 2D material interlayer [graphene; Fig. 1(b), page 2, paragraph 0004] on a growth substrate [SiC substrate; Fig. 1(a), page 2, paragraph 0004].
However, Kim does not explicitly teach:
directly wafer bonding a host substrate to the top surface of the GaN epilayer;
lifting off the GaN epilayers and the host substrate from the 2D material interlayer; and
removing the host substrate from the GaN epilayers to provide a GaN membrane.
Kim and Lee teach:
directly wafer bonding a host substrate to the top surface of the GaN epilayer [Lee, Fig. 2A, para 0032 discloses host substrate 276 attached to top surface of PV layer 274];
lifting off the GaN epilayers and the host substrate from the 2D material interlayer [release of GaN from the graphene layer/substrate; Fig. 1(d), page 2, paragraph 0004 of Kim]; and
removing the host substrate from the GaN epilayers to provide a GaN membrane [Lee, para 0032 discloses removing host substrate 276, thereby exposing 274].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Kim and Lee before the effective filing date of the claimed invention, to include the host substrate as disclosed by Lee into the method of Kim in order to obtain method of manufacturing a semiconductor device which includes attaching a host substrate to the top of a GaN layer.
One of ordinary skill in the art would be motivated to obtain method of manufacturing a semiconductor device which includes attaching a host substrate to the top of a GaN layer to provide the predictable result of providing mechanical stabilization and also cutting costs by providing a reusable platform.
In reference to claim 28, Kim and Lee teach the invention of claim 27.
Kim and Lee do not explicitly teach The fabrication method of claim 27 wherein directly wafer bonding the first host substrate to the GaN epilayer is performed in a wafer bonder.
However, it would have been obvious of one of ordinary skill in the art to use a wafer bonder to bond a host substrate to an epilayer, as using a wafer bonder was well-known in the art to perform such a function.
In reference to claim 29, Kim and Lee teach the invention of claim 27.
Kim teaches The fabrication method of claim 27 wherein lifting off the GaN epilayers includes applying mechanical shear force [release of GaN from the graphene layer/substrate; Fig. 1(d), page 2, paragraph 0004; page 4, paragraph 0001].
Claim(s) 11 and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lee further in view of Kiyama et al. [hereinafter as Kiyama] (US 2015/0349063 A1).
In reference to claim 11, Kim and Lee teach the invention of claim 7.
However, while Kim and Lee teach The fabrication method of claim 7 wherein removing the first host substrate from the GaN epilayer [Lee, para 0032 discloses removing host substrate 276, thereby exposing 274], Kim and Lee do not explicitly teach that this includes wafer grinding the substrate and polishing the epilayer.
Kiyama teaches that this includes wafer grinding the substrate and polishing the epilayer [para 0138 discloses removing substrate and/or nitride film may be done by using grinding and polishing].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Kim, Lee, and Kiyama before the effective filing date of the claimed invention, to include the grinding and polishing as disclosed by Lee into the method of Kim in order to obtain method of manufacturing a semiconductor device which a host substrate is removed from a GaN layer by grinding and polishing.
One of ordinary skill in the art would be motivated to obtain method of manufacturing a semiconductor device which a host substrate is removed from a GaN layer by grinding and polishing to provide the predictable result of reducing manufacturing costs.
In reference to claim 30, Kim and Lee teach the invention of claim 27.
However, while Kim and Lee teach The fabrication method of claim 27 wherein removing the first host substrate from the GaN epilayer [Lee, para 0032 discloses removing host substrate 276, thereby exposing 274], Kim and Lee do not explicitly teach that this includes wafer grinding and polishing the epilayer.
Kiyama teaches that this includes wafer grinding and polishing the epilayer [para 0138 discloses removing substrate and/or nitride film may be done by using grinding and polishing].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Kim, Lee, and Kiyama before the effective filing date of the claimed invention, to include the grinding and polishing as disclosed by Lee into the method of Kim in order to obtain method of manufacturing a semiconductor device which a host substrate is removed from a GaN layer by grinding and polishing.
One of ordinary skill in the art would be motivated to obtain method of manufacturing a semiconductor device which a host substrate is removed from a GaN layer by grinding and polishing to provide the predictable result of reducing manufacturing costs.
Examiner’s Note
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure as follows. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR § 1.111(0).
Keller et al. (US-20240063340-A1) discloses a second host substrate [para 0032].
Krames (US-20070072324-A1) discloses a second host substrate [para 0048].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW CHUNG whose telephone number is (571)272-5237. The examiner can normally be reached M-F 9-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached on 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANDREW CHUNG/
Examiner, Art Unit 2898
Prosecution Insights