DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on September 19, 2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 30, 2023 is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Species 1 (Fig. 2A, Claims 1-19) in the reply filed on April 13, 2026 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Memory Device With Reduced Channel Area
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 7-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsutsumi (US 2020/0251489). Claim 1, Tsutsumi discloses (see annotated Fig. 12) a semiconductor memory device comprising: a word line (46, electrically conductive layers, Para [0220]) including a first area (A1) and a second area (A2) extending continuously from the first area (46 extends continuously from A2 to A1); a first select line (topmost 46 in A1, hereinafter “select1”) overlapping the first area of the word line (select1 overlaps A1); a second select line (topmost 46 in A2, hereinafter “select2”) overlapping the second area of the word line (select2 overlaps A2); a slit (320, drain-select-level isolation, Para [0195]) provided between the first select line and the second select line (320 is between select1 and select2); and a first channel structure (55A, first memory stack structures, Para [0191]) disposed in each of the first select line and the second select line (55A are disposed in each select1 and select2), and extending to penetrate the word line (55A extends to penetrate 46s), wherein the first channel structure (55A) comprises a sidewall adjacent to the slit (labeled 55A comprises sidewall adjacent to 320), with a groove (opening inside 55A, hereinafter “groove”) being formed in the sidewall (groove is formed in sidewall).
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Claim 7, Tsutsumi discloses (see annotated Fig. 12 above) the semiconductor memory device according to claim 1, further comprising: a second channel structure (55B, second memory stack structure, Para [0191]) extending to penetrate each of the first select line and the second select line and to penetrate the word line (55B extends to penetrate select1 and select2 and 46), at a location farther from the slit than the first channel structure (55B is at a location farther from 320 than 55A). Claim 8, Tsutsumi discloses (see annotated Fig. 12 above) the semiconductor memory device according to claim 7, wherein the second channel structure (55B) is disposed inside a closed hole pattern (since 55B doesn’t have a slit it would be closed hole pattern) surrounded by one of the first select line and the second select line (55B is surrounded on one side by select2). Claim 9, Tsutsumi discloses (see annotated Fig. 12 above) the semiconductor memory device according to claim 1, wherein the groove (groove) is formed to include an acute angle or right angle ( as seen in Fig. 12 groove in 55A has right angle).
Allowable Subject Matter
Claims 2-6 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Tsutsumi (US 2020/0251489), Makala (US 2020/0006376), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 2,
Tsutsumi discloses (Fig. 12) a semiconductor memory device comprising: a word line (46, electrically conductive layers, Para [0220]) including a first area (A1) and a second area (A2) extending continuously from the first area (46 extends continuously from A2 to A1); a first select line (topmost 46 in A1, hereinafter “select1”) overlapping the first area of the word line (select1 overlaps A1); a second select line (topmost 46 in A2, hereinafter “select2”) overlapping the second area of the word line (select2 overlaps A2); a slit (320, drain-select-level isolation, Para [0195]) provided between the first select line and the second select line (320 is between select1 and select2); and a first channel structure (55A, first memory stack structures, Para [0191]) disposed in each of the first select line and the second select line (55A are disposed in each select1 and select2), and extending to penetrate the word line (55A extends to penetrate 46s), wherein the first channel structure (55A) comprises a sidewall adjacent to the slit (labeled 55A comprises sidewall adjacent to 320), with a groove (opening inside 55A, hereinafter “groove”) being formed in the sidewall (groove is formed in sidewall).
Tsutsumi does not disclose:
wherein the groove is formed in substantially a V shape.
Regarding Claim 3 (from which claim 4 depends),
Tsutsumi discloses (Fig. 12) a semiconductor memory device comprising: a word line (46, electrically conductive layers, Para [0220]) including a first area (A1) and a second area (A2) extending continuously from the first area (46 extends continuously from A2 to A1); a first select line (topmost 46 in A1, hereinafter “select1”) overlapping the first area of the word line (select1 overlaps A1); a second select line (topmost 46 in A2, hereinafter “select2”) overlapping the second area of the word line (select2 overlaps A2); a slit (320, drain-select-level isolation, Para [0195]) provided between the first select line and the second select line (320 is between select1 and select2); and a first channel structure (55A, first memory stack structures, Para [0191]) disposed in each of the first select line and the second select line (55A are disposed in each select1 and select2), and extending to penetrate the word line (55A extends to penetrate 46s), wherein the first channel structure (55A) comprises a sidewall adjacent to the slit (labeled 55A comprises sidewall adjacent to 320), with a groove (opening inside 55A, hereinafter “groove”) being formed in the sidewall (groove is formed in sidewall).
Tsutsumi does not disclose:
wherein each of the first select line and the second select line comprises a protruding gate portion protruding from each of opposite sides of the first channel structure toward the slit.
Regarding Claim 5,
Tsutsumi discloses (Fig. 12) a semiconductor memory device comprising: a word line (46, electrically conductive layers, Para [0220]) including a first area (A1) and a second area (A2) extending continuously from the first area (46 extends continuously from A2 to A1); a first select line (topmost 46 in A1, hereinafter “select1”) overlapping the first area of the word line (select1 overlaps A1); a second select line (topmost 46 in A2, hereinafter “select2”) overlapping the second area of the word line (select2 overlaps A2); a slit (320, drain-select-level isolation, Para [0195]) provided between the first select line and the second select line (320 is between select1 and select2); and a first channel structure (55A, first memory stack structures, Para [0191]) disposed in each of the first select line and the second select line (55A are disposed in each select1 and select2), and extending to penetrate the word line (55A extends to penetrate 46s), wherein the first channel structure (55A) comprises a sidewall adjacent to the slit (labeled 55A comprises sidewall adjacent to 320), with a groove (opening inside 55A, hereinafter “groove”) being formed in the sidewall (groove is formed in sidewall).
Tsutsumi does not disclose:
wherein the slit is formed in substantially a zigzag shape along a sidewall of each of the first select line and the second select line and the groove.
Regarding Claim 6,
Tsutsumi discloses (Fig. 12) a semiconductor memory device comprising: a word line (46, electrically conductive layers, Para [0220]) including a first area (A1) and a second area (A2) extending continuously from the first area (46 extends continuously from A2 to A1); a first select line (topmost 46 in A1, hereinafter “select1”) overlapping the first area of the word line (select1 overlaps A1); a second select line (topmost 46 in A2, hereinafter “select2”) overlapping the second area of the word line (select2 overlaps A2); a slit (320, drain-select-level isolation, Para [0195]) provided between the first select line and the second select line (320 is between select1 and select2); and a first channel structure (55A, first memory stack structures, Para [0191]) disposed in each of the first select line and the second select line (55A are disposed in each select1 and select2), and extending to penetrate the word line (55A extends to penetrate 46s), wherein the first channel structure (55A) comprises a sidewall adjacent to the slit (labeled 55A comprises sidewall adjacent to 320), with a groove (opening inside 55A, hereinafter “groove”) being formed in the sidewall (groove is formed in sidewall).
Tsutsumi does not disclose:
wherein the channel structure has substantially a fan-shaped cross-sectional structure at a level where each of the first select line and the second select line is disposed.
Regarding Claim 10,
Tsutsumi discloses (Fig. 12) a semiconductor memory device comprising: a word line (46, electrically conductive layers, Para [0220]) including a first area (A1) and a second area (A2) extending continuously from the first area (46 extends continuously from A2 to A1); a first select line (topmost 46 in A1, hereinafter “select1”) overlapping the first area of the word line (select1 overlaps A1); a second select line (topmost 46 in A2, hereinafter “select2”) overlapping the second area of the word line (select2 overlaps A2); a slit (320, drain-select-level isolation, Para [0195]) provided between the first select line and the second select line (320 is between select1 and select2); and a first channel structure (55A, first memory stack structures, Para [0191]) disposed in each of the first select line and the second select line (55A are disposed in each select1 and select2), and extending to penetrate the word line (55A extends to penetrate 46s), wherein the first channel structure (55A) comprises a sidewall adjacent to the slit (labeled 55A comprises sidewall adjacent to 320), with a groove (opening inside 55A, hereinafter “groove”) being formed in the sidewall (groove is formed in sidewall).
Tsutsumi does not disclose:
wherein the groove is formed to include an obtuse angle.
Claims 11-19 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Tsutsumi (US 2020/0251489), Makala (US 2020/0006376), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 11 (from which claims 12-19 depend),
Tsutsumi discloses (Fig. 12) a semiconductor memory device comprising: a word line (46, electrically conductive layers, Para [0220]) including a first area (A1) and a second area (A2) extending continuously from the first area (46 extends continuously from A2 to A1); a first select line (topmost 46 in A1, hereinafter “select1”) overlapping the first area of the word line (select1 overlaps A1); a second select line (topmost 46 in A2, hereinafter “select2”) overlapping the second area of the word line (select2 overlaps A2); a slit (320, drain-select-level isolation, Para [0195]) provided between the first select line and the second select line (320 is between select1 and select2); and a first channel structure (55A, first memory stack structures, Para [0191]) disposed in each of the first select line and the second select line (55A are disposed in each select1 and select2), and extending to penetrate the word line (55A extends to penetrate 46s), wherein the first channel structure (55A) comprises a sidewall adjacent to the slit (labeled 55A comprises sidewall adjacent to 320), with a groove (opening inside 55A, hereinafter “groove”) being formed in the sidewall (groove is formed in sidewall).
Tsutsumi does not disclose:
wherein each of the first select line and the second select line comprises a first protruding gate portion and a second protruding gate portion protruding toward the slit with the first channel structure interposed therebetween.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Makala (US 2020/0006376) discloses (Fig. 17A) word lines 46, channels 52/54/56/69/62 with a slit where 64 is formed. Makala does not disclose wherein the first channel structure comprises a sidewall adjacent to the slit, with a groove being formed in the sidewall.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GUSTAVO G RAMALLO/Examiner, Art Unit 2812
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