DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/23/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by
Murasaka et al. (WO 2016009924 A1), hereinafter called Murasaka.
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Annotated Fig. 3 for ease of reference.
Regarding claim 1, Murasaka discloses in annotated Fig. 3, an operational amplifier (annotated Fig. 3) comprising:
a first load (L1, Fig. 3);
a second load (L2, Fig. 3);
a first switching transistor group (G1);
a second switching transistor group (G2); and
a tail current source (ITAIL, Fig. 3),
wherein
a first end (E1) of the first switching transistor group (G1) is connected to a first output end (OUTM) of the operational amplifier, and is connected to a power supply (annotated VDD) of the operational amplifier by using the first load (L1), and
a second end (E2) of the first switching transistor group is grounded by using the tail current source (ITAIL, it is noted that Fig. 3 of Murasaka having similarly arrangement to the Fig. 3 of the examining application);
a first end (E3) of the second switching transistor group (G2) is connected to a second output end (OUTP) of the operational amplifier, and is connected to the power supply (VDD) by using the second load (L2), and
a second end (E4) of the second switching transistor group is grounded by using the tail current source (ITAIL);
the first switching transistor group (G1) and the second switching transistor group(G2) comprise a same quantity (same type transistor) of at least two input adjustment units (AU1 and AU2), and an input end (gate terminal of M1 and gate terminal of M2) of each of the at least two input adjustment units (AU1 and AU2) is connected to an input signal (input signal, INP, INM); and the input signal connected to each of the at least two input adjustment units is adjustable.
Allowable Subject Matter
Claims 2-10 & 14-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11-12 & 13 are allowed.
Upon conclusion of a comprehensive search of the pertinent prior art, the Office indicates that the claims are allowable.
The prior art when taken alone, or, in combination, cannot be construed as reasonably teaching or suggesting all of the elements of the claimed invention as arranged, disposed, or provided in the manner as claimed by the Applicant. Added primarily for emphasis, the claim recitations “an input end of the low voltage differential signal generation circuit is connected to the power supply, and a feedback signal end of the low voltage differential signal generation circuit is connected to the first output end of the operational amplifier or the second output end of the operational amplifier; the low voltage differential signal generation circuit is configured to output a common-mode signal, and the common-mode signal is a first input signal of the operational amplifier; and an output end of the low voltage differential signal generation circuit is configured to output a low voltage differential signal” in Claim 11 and “determining a target gain; and determining an adjustment signal based on the target gain, and sending the adjustment signal to the first switching transistor group and the second switching transistor group, wherein the adjustment signal is for adjusting the input signal connected to each input adjustment unit” in Claim 13 are not found in the prior art of record.
Claim 12 is allowable as being dependent of claim 11.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/KHIEM D NGUYEN/Examiner, Art Unit 2843