Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of group I, claims 1-6, 11-16 in the reply filed on 2/5/26 is acknowledged. Claims 12-19 are withdrawn from further consideration by the examiner, 37 C.F.R. 1.142(b) as being drawn to a non-elected invention.
Information Disclosure Statement
The information disclosure statements filed 11/8/23; 11/8/23; 6/30/23 have been considered.
Oath/Declaration
Oath/Declaration filed on 7/6/23 has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-10 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Dey et al. (U.S. Patent Publication No. 2023/0361222).
Referring to figures 1-12, Dey et al. teaches a microelectronic device, comprising:
a semiconductor substrate (102(104/106/108));
a III-N semiconductor layer (110) over the semiconductor substrate, with a substrate via opening (804) extending through the III-N semiconductor layer to the semiconductor substrate;
a substrate contact pad (124) in the substrate via opening, contacting the semiconductor substrate and making an electrical connection to the semiconductor substrate (102(104/106/108), see figure 12);
a dielectric layer (140/160) over the substrate contact pad in the substrate via opening, the dielectric layer having a planar surface over the substrate via opening (see figure 12); and
an interconnect metal level (144/154) over the dielectric layer (see figure 12).
Regarding to claim 2, the interconnect metal level extends to an input/output terminal of the microelectronic device (174, see figure 12).
Regarding to claim 3, the interconnect metal level (164/174) is thicker than the substrate contact pad (124, see figure 12).
Regarding to claim 6, a singulation lane seal extending over an edge of the III-N semiconductor layer and onto the semiconductor substrate in singulation lanes around a perimeter of the microelectronic device (see paragraph# 21).
Regarding to claim 7, the substrate via opening (804) is under a scribe seal structure proximate to a perimeter of the III-N semiconductor layer (see paragraph# 21, figure 12).
Regarding to claim 8, wherein singulation lanes at a perimeter of the microelectronic device are free of the III-N semiconductor layer (see paragraph# 21, figure 12).
Regarding to claim 9, the substrate contact pad (124) extends above the III-N semiconductor layer adjacent to the substrate via opening (see figure 12).
Regarding to claim 10, the substrate contact pad fills the substrate via opening, and a top surface of the substrate contact pad is planar above the substrate via opening (see figure 12).
Claim(s) 1-2, 9-10, 20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Wang et al. (U.S. Patent Publication No. 2024/0213333).
Referring to figures 1a-4I, Wang et al. teaches a microelectronic device, comprising:
a semiconductor substrate (101a);
a III-N semiconductor layer (101b) over the semiconductor substrate, with a substrate via opening (134) extending through the III-N semiconductor layer to the semiconductor substrate;
a substrate contact pad (136/137) in the substrate via opening, contacting the semiconductor substrate and making an electrical connection to the semiconductor substrate (101a, see figure 1S);
a dielectric layer (146) over the substrate contact pad in the substrate via opening, the dielectric layer having a planar surface over the substrate via opening (see figure 1S); and
an interconnect metal level (147) over the dielectric layer (see figure 1S).
Regarding to claim 2, the interconnect metal level extends to an input/output terminal (249) of the microelectronic device.
Regarding to claim 9, the substrate contact pad (136/137) extends above the III-N semiconductor layer adjacent to the substrate via opening (see figure 1S).
Regarding to claim 10, the substrate contact pad (136/137) fills the substrate via opening, and a top surface of the substrate contact pad is planar above the substrate via opening (see figure 1S).
Regarding to claim 20, a microelectronic device, comprising: a semiconductor substrate; a III N semiconductor layer (101b) over the semiconductor substrate, with a substrate via opening (134) extending through the III N semiconductor layer to the semiconductor substrate; and a substrate contact pad (137) including primarily tungsten (see paragraph# 48) in the substrate via opening, contacting the semiconductor substrate and making an electrical connection to the semiconductor substrate (101a, see figure 1S).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dey et al. (U.S. Patent Publication No. 2023/0361222) or Wang et al. (U.S. Patent Publication No. 2024/0213333) applied in claim(s) 1-3, 6-10, 20 above.
Referring to figures 1-12, Dey et al. teaches a microelectronic device, comprising:
a semiconductor substrate (102(104/106/108));
a III-N semiconductor layer (110) over the semiconductor substrate, with a substrate via opening (804) extending through the III-N semiconductor layer to the semiconductor substrate;
a substrate contact pad (124) in the substrate via opening, contacting the semiconductor substrate and making an electrical connection to the semiconductor substrate (102(104/106/108), see figure 12);
a dielectric layer (140/160) over the substrate contact pad in the substrate via opening, the dielectric layer having a planar surface over the substrate via opening (see figure 12); and
an interconnect metal level (144/154) over the dielectric layer (see figure 12).
However, the reference does not clearly teach the substrate via opening has a width at the semiconductor substrate that is less than two times a thickness of the III-N semiconductor layer (in claim 4), the substrate via opening has a length at the semiconductor substrate, perpendicular to the width, that is less than two times the thickness of the III-N semiconductor layer (in claim 6).
The selection of the thickness is obvious because it is a matter of determining optimum process condition by routine experimentation with a limited number of species. ln re Jones, 162 USPQ 224 (CCPA 1955)(the selection of optimum ranges within prior art general conditions is obvious) and In re Boesch, 205 USPQ 215 (CCPA 1980)(discovery of optimum value of result effective variable in a known process is obvious). In such a situation, applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to prior art range. See M.P.E.P 2144.05 III. In particular, Dey et al. suggest that the thickness can be optimized (see figure 12). It would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was made to optimize the thickness of the III-V semiconductor layer, since it has been held that where the general conditions of a claim are disclosed in the prior art (i.e.- thickness of the III-V semiconductor layer), discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form the specific thickness of the III-V semiconductor layer in Dey et al. and Wang et. because choosing an optimum thickness for a layer is known in the semiconductor art to form an optimum semiconductor device.
Claim 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dey et al. (U.S. Patent Publication No. 2023/0361222) or Wang et al. (U.S. Patent Publication No. 2024/0213333) applied in claim(s) 1-3, 6-10, 20 above in view of Wang et al. (U.S. Patent Publication No. 2019/0019770).
Referring to figures 1-12, Dey et al. teaches a microelectronic device, comprising:
a semiconductor substrate (102(104/106/108));
a III-N semiconductor layer (110) over the semiconductor substrate, with a substrate via opening (804) extending through the III-N semiconductor layer to the semiconductor substrate;
a substrate contact pad (124) in the substrate via opening, contacting the semiconductor substrate and making an electrical connection to the semiconductor substrate (102(104/106/108), see figure 12);
a dielectric layer (140/160) over the substrate contact pad in the substrate via opening, the dielectric layer having a planar surface over the substrate via opening (see figure 12); and
an interconnect metal level (144/154) over the dielectric layer (see figure 12).
However, the reference does not clearly the substrate via opening has sloped sides having a sidewall angle greater than 15 degrees from vertical.
Chang et al. teaches substrate (102) via opening (108) has sloped sides having a sidewall angle greater than 15 degrees from vertical (see figure 2a). It would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was made to optimize sidewall angle, since it has been held that where the general conditions of a claim are disclosed in the prior art (i.e.- sidewall angle), discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form the specific sidewall angle in Dey et al. and Wang et. as taught by Chang et al. because it is known in the art to achieve for deep via holes.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893