DETAILED ACTION
Claims 1-15 and 18-22 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 3, 2025, has been entered.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Drawings
Replacement FIG.4B submitted on April 3, 2025, is objected to because it is inconsistent with FIG.3B. Specifically, the examiner questions why 424 is inputted into 480? FIG.4B shows element 480 receiving three word inputs 422, 424, 426. Element 480, as the examiner understands it, is illustrated in FIG.3B. However, FIG.3B does not show a third word input. Clarification is needed.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or appropriate clarification, are required in reply to the Office action to avoid abandonment of the application. Please ensure any replacement is in only black and white to avoid pixelation and further objection. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 1 is objected to because of the following informalities:
In line 2, replace “A” with --a--.
Claim 10 is objected to because of the following informalities:
In line 7, insert --circuit-- after “element”.
Appropriate correction is required.
Claim Interpretation
In response to applicant’s claiming of circuit(s), 112(f) is no longer invoked and broadest reasonable interpretation applies for all claim limitations.
In claims 21-22, a deinterleaved half is interpreted based on the common meaning of “deinterleaved”. As such, a given half in claims 21-22 was initially interleaved before being subsequently deinterleaved. As such, the claims require interleaving data, deinterleaving the interleaved data, and then interleaving the deinterleaved data.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-15 and 18-22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Per MPEP 2164.01(a), there are many factors to be considered when determining whether there is sufficient evidence to support a determination that a disclosure does not satisfy the enablement requirement and whether any necessary experimentation is “undue.” These factors include, but are not limited to:
(A) The breadth of the claims;
(B) The nature of the invention;
(C) The state of the prior art;
(D) The level of one of ordinary skill;
(E) The level of predictability in the art;
(F) The amount of direction provided by the inventor;
(G) The existence of working examples; and
(H) The quantity of experimentation needed to make or use the invention based on the content of the disclosure.
In re Wands, 858 F.2d 731, 737, 8 USPQ2d 1400, 1404 (Fed. Cir. 1988)
Each of the independent claims sets forth to interleave a word corresponding to the previously sent bit sequence and a word corresponding to the output bit sequence (factor A). From paragraph [0001] of applicant’s specification, the nature of the invention is to reduce power during data transmission by reducing the number of bits toggled between a previously sent bit sequence and a current output bit sequence (factor B). However, one of ordinary skill in the art would not understand how to make and use the claimed interleaving based on applicant’s description thereof. Paragraph [0017] only vaguely sets forth that two words can be interleaved, but does not explain how, or what the words actually are (it is not clear if applicant is interleaving the aforementioned sequences themselves, or words corresponding to the sequences). The only other paragraph discussing the interleaving is paragraph [0036], which states that the interleaving ensures that all bits of the words are sent in the same bit-time and allowing the scheme. This is unclear to the examiner as the power savings described above is achieved by sending a previous sequence first, and subsequently sending a current sequence that limits toggling with respect to the previous sequence. It has not been explained how the interleaving allows for both (1) sending all bits at once (assuming this is what bit-time means) and (2) the power savings that is disclosed to occur between consecutively-sent words. To add to the confusion, the only FIG relating to interleaving is FIG.4B, which has been changed twice since filing due to lack of clarity. The swizzler/interleaver is only generically shown as box 474 and does not illustrate how the interleaving actually occurs. It is also not clear what the previously sent sequence and the current sequence are in FIG.4B. Based on the description of FIG.3B, it appears that the previous sequence would be that in 426 or 428, which is re-inputted into circuits 480 or 481 for XORing with the current sequence 422 or 424. But, it is not 422 that is interleaved with 426, nor is it 424 that is interleaved with 428. In general, the interleaving process is unclear to one of ordinary skill in the art based on the minimal disclosure related thereto, based on the lack of any working example provided by applicant, based on the various changes made throughout prosecution to FIG.4B, and based on the lack of clarity as to what the components of FIG.4B actually represent (factors D, F, and G). The state of the prior art includes teachings of interleaving separate data items before transmission to improve error correction (see prior art cited below). However, this does not assist in enabling the claimed/disclosed interleaving in combination with realizing power savings when sending consecutive bit sequences (factor C). Though the computer arts are generally predictable, this general predictability does not allow one to fill in the blanks left by applicant to make and use this particular interleaving (factor E). Consequently, the examiner asserts that the totality of evidence suggests that applicant has not enabled one of ordinary skill to make/use an invention that realizes the power savings desired by applicant while interleaving.
Further, with respect to claims 21-22, applicant claims that deinterleaved words are interleaved. Applicant has not explained in any way what it means for the data to be deinterleaved. It is only nominally mentioned in paragraph [0036]. The common definition of deinterleaving is to reverse interleaving or to convert from an interleaved format. Applicant never mentions any initial interleaving prior to deinterleaving, only for interleaving to occur again. The examiner is initially not clear on whether applicant meant non-interleaved instead of deinterleaved. Again, there are no working examples or direction provided by applicant and no prior art teaching interleaving/deinterleaving to reduce power by reducing toggling. As such, based on the totality of evidence, one of ordinary skill in the art would not know how to make and use this invention.
All dependent claims are rejected due to their dependent on a non-enabled claim.
Claims 18-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 18 has been amended to set forth that an input bit sequence from a plurality of data element circuits is biased. The examiner cannot find support for this feature and applicant has not pointed to any such support. FIG.3B shows biasing input data at XOR gate 382, which is part of the data element circuit. Thus, the biasing occurs within the data element circuit itself, and is not performed on a sequence from the data element circuit. Does applicant mean --by-- or --using-- instead of “from”? Please address this new matter.
Claims 19-20 are rejected due to their dependence on a claim lacking adequate written description.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-15 and 18-22 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Referring to claim 18 and step 1 of the Alice framework, the claim recites a process.
Regarding step 2A (prong 1) of the Alice framework, claim 18 recites an abstract idea in the grouping of mathematical concepts and/or mental processes. Specifically, the claim recites “biasing an input bit sequence such that at most half of the biased bit sequence includes logic 1 values,” “producing an output bit sequence from an XOR of the biased bit sequence and a previously sent bit sequence, wherein the previously sent bit sequence corresponds to a first half of two data words and the output bit sequence corresponds to a second half of the two data words”, and “producing a sending bit sequence based on interleaving the two data words”. The biasing step, per the specification, is merely an inversion (XOR) of a bit sequence, where each bit is flipped (e.g. see FIG.2B, where value 242 is biased/inverted such that the 1s are changed to 0s and the 0s are changed to 1s. Applicant uses XOR gate 382 (FIG.3B) to perform the inversion). The inverting of any binary value having half or more of its bits equaling 1 will result in at most half of the biased/inverted value’s bits including logic 1 values. The first producing step involves performing an XOR on two binary values (this is shown in FIG.2B, and the XOR gate responsible is XOR gate 384 in FIG.3B). XOR operations used in the mathematical field of Boolean algebra. Applicant may visit Wikipedia’s “Boolean Algebra” (not formally cited herewith) for more information. Note that a “previously sent” is merely a label. A list of data to be transmitted in order can be presented to a human, and a previously-sent item would be any that precedes a subsequent data item. Thus, the math can be performed on values presented to a human in a list in the order given. Finally, the second producing step amounts to at least a mental process (and potentially a mathematical concept) that can be performed in the mind or with pen and paper. For instance, a human supplied with two binary values (e.g. 0000 and 1111) could mentally interleave them (e.g. alternate the bits) to realize 01010101.
Regarding step 2A (prong 2) of the Alice framework, claim 18 recites additional elements of the input bit sequence being “from a plurality of data element circuits”, the second producing being performed “using a swizzler circuit”, and “transmitting the sending bit sequence”. However, data element circuits and a swizzler circuit are generic computer components in a generic computer used as a tool to perform the abstract idea. Of note, a circuit named “swizzler” is nothing more than a generic circuit claimed to perform a mental process of interleaving two values. Furthermore, the act of transmitting the result of the abstract idea is deemed to be insignificant post-solution activity that is understood to be incidental to the primary abstract process and that amounts to a mere nominal/tangential addition to the claim. Thus, these additional elements fail to integrate the abstract idea into a practical application (see MPEP 2106.04(d)(I)).
Regarding step 2B, using a generic computer as a tool to perform the abstract idea does not amount to significantly more, per the courts (see MPEP 2106.05(I)(A)). Further, from MPEP 2106.05(d)(II), transmitting data over a network has been specifically recognized by the courts as a well-known, routine, and conventional function when recited in a highly generic manner or as insignificant extra-solution activity. Thus, the additional elements, considered individually and in combination, do not amount to significantly more.
For these reasons, claim 18 is not patent-eligible under 101.
Referring to claim 19, the producing and unbiasing steps are again a mathematical concept that amount to the reverse of the math of claim 18. That is, claim 18 performs math to transform an input bit sequence into a sending bit sequence, and claim 19 performs math to transform the sending bit sequence back into the input bit sequence. This reverse math is again an abstract idea. The receiving step, using flip flop circuits, also does not integrate the abstract idea into a judicial exception, nor does it amount to significantly more because recitation of receiving binary data into flip-flops constitutes receiving in a highly generic manner (using generic computer components). That is, the receiving is deemed to be insignificant extra-solution activity that is recited in a highly generic way (using fundamental computer storage components such that when the data is received, it is stored). The courts have deemed such activity, alone and in combination with the other additional elements of claim 18, to not integrate a judicial exception into a practical application and to not amount to significantly more.
Referring to claim 20, the biasing and unbiasing based on an inversion indicator are mathematical/mental processes. That is, in order to know whether or not unbiasing is required to get to the original data, an indication that biasing occurred is required. For instance, a human will only unbias if the biasing occurs (thus, there is some indication present that indicates biasing has occurred). As described above, an additional step of transmitting (in this claim transmitting an indication) is insignificant extra-solution activity that, per the courts, does not integrate the abstract idea into a practical application or amount to significantly more.
Claims 21-22 are directed to additional mental/math processes that a human can perform in their mind. A human can interleave and deinterleave data with or without the aid of pen and paper.
Referring to claim 1 and step 1 of the Alice framework, the claim recites a machine.
Regarding step 2A (prong 1) of the Alice framework, claim 1 recites an abstract idea in the grouping of mathematical concepts and/or mental processes. Specifically, the claim recites [generating] “an output bit sequence by toggling at most half of a number of bits from a previously sent bit sequence and the previously sent bit sequence corresponds to a first half of two data words and the output bit sequence corresponds to a second half of the two data words” and “interleave the two data words”. As described above, toggling/inverting is a concept in Boolean algebra. And, interleaving is at least a mental process that can be performed in the human mind and/or with pen/paper. The rest is mere labeling of data.
Regarding step 2A (prong 2) of the Alice framework, claim 1 recites additional elements of “a first plurality of data element circuits each configured to send a bit based on an input bit sequence” (the collective bits sent forming an output bit sequence) by performing the toggling. However, these circuits are generic computer components. A circuit to send a bit is a generic computer component to perform insignificant post-solution activity (transmitting data), which, per the courts, does not integrate the abstract idea into a practical application (as described above for claim 18). Furthermore, a swizzler circuit coupled to the first plurality of data element circuits is also highly generic as described above (it is a generic circuit called “swizzler”) and, thus, a generic computer is still being used as a tool to perform the interleaving. As such, the circuit does not integrate the abstract idea into a practical application.
Regarding step 2B, the additional elements, considered individually and in combination, do not amount to significantly more. From MPEP 2106.05(d)(II), sending data over a network using a generic circuit has been specifically recognized by the courts as a well-known, routine, and conventional function when recited in a highly generic manner or as insignificant extra-solution activity. Recitation of transmitting/sending using circuits constitutes transmitting in a highly generic manner. Also, using a generic computer component as a tool to perform the math/mental process does not amount to significantly more, per the courts (see MPEP 2106.05(I)(A)).
For these reasons, claim 1 does not amount to significantly more than the abstract idea.
Claims 2-3 are not patent eligible for similar reasoning given in the rejection of claim 1, because flip flops and XOR gates are generic computer components, and, more specifically, fundamental building blocks of computers. These are just generic computer components to perform the math and, thus, they do not integrate the abstract idea into a practical application, not do they amount to significantly more.
Claim 4 recites an additional element of a control circuit to control the data element circuits to bias the input bit sequence. As previously described, the biasing is simply an inversion performed by XOR gate 382. As claimed, a control circuit is simply a generic computer component used to implement this math, and thus, it does not integrate the abstract idea into a practical application, or amount to significantly more.
Claim 5 includes the mental process of detecting that the input bit sequence includes more logic 1 values than logic 0 values. This is a mere judgment/evaluation of a binary value. The additional element of a generic control circuit to perform this detection, alone or in combination with the others, does not integrate the abstract idea into a practical application, or amount to significantly more, because it is part of a generic computer used as a tool to perform the abstract idea.
Claim 6 sets forth an abstract idea of sending an indication for inverting the input bit sequence in response to the detecting, which constitutes a mental process than dictates whether a human should perform inversion. Paragraph 29 explains that inversion is performed when more than half the bits in the bit sequence are equal to 1. A human can look at a binary value and count the number of bits that are 1. If that number is more than half, then a “Yes” signal/indication is generated in the brain; otherwise a “No” signal/indication is generated. When the “Yes” signal is generated, this means the human may then perform the inversion math. The additional element of the control circuit to send this indication is a generic component that allows a computer to be used as a tool to carry out the abstract idea. As a result, it does not integrate the abstract idea into a practical application, nor does it amount to significantly more.
Claims 7-9 recite additional generic circuits that do not integrate into a practical application, nor amount to significantly more because they are generic computer components that allow a computer to perform the reverse math to obtain the original data item.
Referring to claim 10 and step 1 of the Alice framework, the claim recites a machine.
Regarding step 2A (prong 1) of the Alice framework, claim 10 recites an abstract idea in the grouping of mathematical concepts. Specifically, the claim recites [generating] “the output bit sequence by toggling at most half of a number of bits from a previously sent bit sequence, wherein the previously sent bit sequence corresponds to a first half of two data words and the output bit sequence corresponds to a second half of the two data words” and “interleave the two data words” and “interleave the two data words”. As described above, toggling/inverting is a concept in Boolean algebra, and interleaving is a mental process (and potentially math).
Regarding step 2A (prong 2) of the Alice framework, claim 10 recites additional elements of “a physical memory”, “at least one physical processor coupled to the physical memory comprising”, “a first plurality of data element circuits each configured to send a bit of an output bit sequence based on an input bit sequence”, “a second plurality of data element circuits each configured to receive the bit of the output bit sequence from a corresponding data element of the first plurality of data element circuits”, “a control circuit configured to control the first plurality of data element circuits to bias the input bit sequence”, and “a swizzler circuit coupled to the first plurality of data element circuits”. The circuits are claimed generically and do not integrate the abstract idea into a practical application because they are generic computer components that allow a generic computer to perform the abstract idea. Additionally, the memory and at least one physical processor are known generic computer components to implement the abstract idea and thus also do not integrate the abstract idea into a practical application. Also, the sending and receiving of a bit (using generic computer components) is extra-solution activity that does not integrate the abstract idea into a practical application.
Regarding step 2B, the additional elements, considered individually and in combination, do not amount to significantly more. From MPEP 2106.05(d)(II), sending/receiving data over a network using generic circuitry has been specifically recognized by the courts as a well-known, routine, and conventional function when recited in a highly generic manner or as insignificant extra-solution activity. Recitation of transmitting/sending using generic circuitry constitutes transmitting in a highly generic manner. Also, using a generic computer component as a tool to perform the math does not amount to significantly more, per the courts (see MPEP 2106.05(I)(A)).
For these reasons, claim 10 is not patent eligible under 101.
Claims 11-12 are not patent eligible for similar reasoning given above.
Referring to claim 13, for similar reasoning given above with respect to claims 4-5, the counting of 1s in a sequence is an abstract idea and a generic control circuit for performing the counting (and the control of biasing by inverting) does not integrate the abstract idea into a practical application nor does it amount to significantly more.
Claims 14-15 are not patent eligible for similar reasoning given above with respect to claims 6 and 20, respectively.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al., “A 50% Noise Reduction Interface Using Low-Weight Coding”, in view of Wikipedia, “Error correction code”.
Referring to claim 1, Nakamura has taught a device comprising:
a first plurality of data element circuits each configured to send a bit based on an input bit sequence (see FIG.3(a) and note that the lower eight empty rectangles, in the vertical stack of rectangles, along with the selector “Sel” (and input logic thereto) are the plurality of data element circuits. Each of these, as shown in the exploded view at the top, includes an XOR gate that outputs to a register. The register outputs to the XOR gate and also sends a bit, whose value is ultimately based on the input sequence on the bus at the far left of FIG.3(a), to a receiver shown in FIG.3(b)), wherein the first plurality of data element circuits sends an output bit sequence by toggling at most half of a number of bits from a previously sent bit sequence (see FIG.3(a) and section 3. The XOR gates toggle the previously sent bit sequence from the register. The toggling only affects at most half of the previously sent bit sequence based on the value selected by “Sel”. That is, if there are five or more 1s in the 8b input value, the majority voter detects this and controls “Sel” to select and output the inverse of the 8b input so that no more than half of the previous sequence’s bits are changed. As an example, assume the 8b input value is 00000111 and the previous value in the register R is 11100000. The majority voter determines that the number of 1s in the 8b input value is not greater than N/2 (8/2 = 4). Thus, “Sel” selects the non-inverted input (00000111) and XORs it with 11100000 to get a transmitted value of 11100111 (only three toggles of the previous sequence. If the values are instead 11000111 and 11100000, respectively, “Sel” will select the inverted input since there are five 1s, which is greater than 8/2 = 4. Thus, 00111000 is XOR’d with 11100000 to send a value of 11011000 (again, only three toggles). When the 8b input has four 1s, only 4 bits will be toggled in the previous sequence and, in fact, this is the highest amount of toggling that can occur) and the previously sent bit sequence corresponds to a first half of two data words and the output bit sequence corresponds to a second half of two data words (the two sequences are different sequences; thus, one is a first word to two words and the other is a second word of the two words).
Nakamura has not taught a swizzler circuit coupled to the first plurality of data element circuits and configured to interleave the two data words. However, Wikipedia has taught interleaving of consecutive words prior to transmission to mitigate the effects of burst errors by distributing them more uniformly, which could result in easier error correction. See the “Interleaving” sections on pp.7-9. As a result, in order to improve error correction in Nakamura’s transmission system, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nakamura to include a swizzler circuit coupled to the first plurality of data element circuits and configured to interleave the two data words.
Referring to claim 4, Nakamura, as modified, has taught the device of claim 1, further comprising a control circuit configured to control the first plurality of data element circuits to bias the input bit sequence such that at most half of the biased bit sequence includes logic 1 values (as explained in the rejection of claim 1, the majority voter is the control circuit which controls whether the input is biased or not, i.e., by controlling “Sel” to select either the inverted or non-inverted input so as to only toggle up to four bits of the previous sequence).
Referring to claim 5, Nakamura, as modified, has taught the device of claim 4, wherein the control circuit is configured to detect that the input bit sequence includes more logic 1 values than logic 0 values (again, see the rejections of claims 1 and 4. The majority voter detects when there are more 1s than 0s).
Referring to claim 6, Nakamura, as modified, has taught the device of claim 5, wherein the control circuit is configured to send an indication to the first plurality of data element circuits for inverting the input bit sequence in response to the detecting (see the signal into the top of “Sel” in FIG.3(a). This signal indicates whether inversion occurs or not. If there are more 1s than 0s in the input, then an inversion indication is sent to select input 1 of “Sel”; otherwise, input 0 is selected (and the input is not inverted)).
Referring to claim 7, Nakamura, as modified, has taught the device of claim 1, further comprising a second plurality of data element circuits each configured to receive the bit of the output bit sequence from a corresponding data element circuit of the first plurality of data element circuits (see FIG.3(b). The second plurality of elements are the eight lower empty rectangles in the stack of rectangles, which are comprises of the circuitry shown in the exploded view at the top. The register (which is an equivalent of a flip-flop as explained in the rejection of claim 1) receives a corresponding sent bit from one of the plurality of sending data elements).
Referring to claim 18, Nakamura has taught a method comprising:
biasing an input bit sequence from a plurality of data element circuits such that at most half of the biased bit sequence includes logic 1 values (see the rejections of claims 1 and 4. Note that when the data element circuits are interpreted to additionally include the inverter and wiring thereto of FIG.3(a), the input bit sequence is from the data element circuits);
producing an output bit sequence from an XOR of the biased bit sequence and a previously sent bit sequence (see FIG.3(a) and note that that the XOR gates XOR the biased sequence from the selector “Sel” and the previously sent sequence from register R. The result is an output sequence), wherein the previously sent bit sequence corresponds to a first half of two data words and the output bit sequence corresponds to a second half of two data words (as described in the rejection of claim 1, the two sequences are different sequences; thus, one is a first word to two words and the other is a second word of the two words).
Nakamura has not taught producing, using a swizzler circuit, a sending bit sequence based on interleaving the two data words; and transmitting the sending bit sequence. However, such is obvious for reasons set forth in the rejection of claim 1.
Referring to claim 19, Nakamura, as modified, has taught the method of claim 18, further comprising:
receiving, via a second plurality of data element circuits, the sending bit sequence (see FIG.3(b) and note that registers R receive the sending bit sequence from FIG.3(a));
producing a currently received bit sequence from an XOR of the sending bit sequence and a previously received bit sequence (see FIG.3B and note that the XOR gate XORs the sending bit sequence (lower input to XOR) and the previously received sequence in register R (top input to XOR) to generate a received bit sequence); and
unbiasing the currently received bit sequence (the received bit sequence output by the XOR gates is then unbiased by going through the inverter and being selected by the selector “Sel” in FIG.3(b) in response to “SIGN”, which is indicative of inversion when inversion took place in FIG.3(a)).
Referring to claim 20, Nakamura, as modified, has taught the method of claim 19, wherein:
biasing the input bit sequence further comprises inverting the input bit sequence (see the inverter at the bottom left of FIG.3(a));
transmitting the sending bit sequence further comprises sending an inversion indicator in response to inverting the input bit sequence (see FIGs.3(a)-(b) and note the SIGN indicator, which is indicative of biasing/inversion. This is transmitted to the receiving side to control unbiasing); and
unbiasing the currently received bit sequence further comprises inverting the currently received bit sequence in response to receiving the inversion indicator (as described above and shown in FIG.3(b), the SIGN indicator is used to control the selector “Sel” to select the inverted received sequence).
Claims 2-3 and 8-15 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura in view of Wikipedia and the examiner’s taking of Official Notice.
Referring to claim 2, Nakamura, as modified, has taught the device of claim 1, wherein each of the first plurality of data element circuits comprises an XOR gate (see FIG.3(a) and section 3). Nakamura has further taught a register circuit coupled to the XOR gate (FIG.3(a)) instead of a flip flop circuit coupled to the XOR gate. However, it was well known in the art before applicant’s invention to implement a register with a flip-flop, which is a stable basic storage element that is a fundamental building block of digital electronics systems. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nakamura such that the register of FIG.3(a) is implemented via flip-flop.
Referring to claim 3, Nakamura, as modified, has taught the device of claim 2, wherein for each of the first plurality of data element circuits the XOR gate has inputs including a previously sent bit of the previously sent bit sequence from the flip flop circuit (from FIG.3(a), the value from R) and a currently sending bit based on the input bit sequence (a bit from selector “Sel”) and an output to the flip flop circuit (that value from XOR to R).
Referring to claim 8, Nakamura, as modified, has taught the device of claim 7, wherein each of the second plurality of data element circuits comprises an XOR gate (see FIG.3(b) and section 3). Nakamura has further taught a register circuit coupled to the XOR gate (FIG.3(b)) instead of a flip flop circuit coupled to the XOR gate. However, for similar reasoning given in the rejection of claim 2, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nakamura such that the register of FIG.3(b) is implemented via flip-flop.
Referring to claim 9, Nakamura, as modified, has taught the device of claim 8, wherein for each of the second plurality of data element circuits the XOR gate has inputs including a previously received bit of a previously received bit sequence from the flip flop circuit (FIG.3(b), the value from R) and a currently received bit of the output bit sequence (FIG.3(b), the value on the lower input to the XOR).
Referring to claim 10, Nakamura has taught a system comprising:
a first plurality of data element circuits each configured to send a bit of an output bit sequence based on an input bit sequence (again, see FIG.3(a) and the explanation in the rejection of claim 1);
a second plurality of data element circuits each configured to receive the bit of the output bit sequence from a corresponding data element of the first plurality of data element circuits (again, see FIG.3(b) and the explanation in the rejection of claim 7); and
a control circuit configured to control the first plurality of data element circuits to bias the input bit sequence such that the first plurality of data element circuits sends the output bit sequence by toggling at most half of a number of bits from a previously sent bit sequence (again, see FIG.3(a) and the explanations in the rejections of claims 1 and/or 4), wherein the previously sent bit sequence corresponds to a first half of two data words and the output bit sequence corresponds to a second half of two data words (as described in the rejection of claim 1, the two sequences are different sequences; thus, one is a first word to two words and the other is a second word of the two words).
Nakamura has not taught a swizzler circuit coupled to the first plurality of data element circuits and configured to interleave the two data words. However, such is obvious for reasons set forth in the rejection of claim 1.
Nakamura has also not taught that the system comprises a physical memory and at least one physical processor coupled to the physical memory and comprising the above components. However, the first sentence of Nakamura indicates desire to increase performance in computer systems. A computer system was well known in the art before applicant’s invention to comprise a physical memory to store data and at least one physical processor to process and communicate data on behalf of a user. Any computer/processor that communicates data to a receiving point can benefit from the reduced bit toggling/transitions of Nakamura to reduce noise and power (see section I). As a result, in order to reduce noise and power in a processor that is part of a basic computer system to store and process data, it would have been obvious to one of ordinary skill in the art to modify Nakamura such that the system comprises a physical memory and at least one physical processor coupled to the physical memory and comprising the above components.
Claim 11 is rejected for similar reasoning as claims 2-3 and 8-9.
Claim 12 is rejected for similar reasoning as claim 4.
Referring to claim 13, Nakamura, as modified, has taught the system of claim 10, wherein the control circuit comprises a counter for counting logic 1 values in the input bit sequence (see the Majority Voter of FIG.3(a)) and the control circuit is configured to detect, using the counter, that the input bit sequence includes more logic 1 values than logic 0 values (see the rejection of claims 1 and 4-5. That is, the majority voter counts the number of 1s and, detects when the number of 1s is greater than N/2 (N being the number if bits in the input bit sequence)).
Claim 14 is rejected for similar reasoning as claim 6.
Referring to claim 15, Nakamura, as modified, has taught the system of claim 14, wherein the second plurality of data element circuits is configured to invert the received bit sequence in response to the indication (the SIGN indication, which is indicative of inversion on the sending side (FIG.3(a)), causes the selected “Sel” on the receiving side (FIG.3(b)) to invert the received bit sequence).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura in view of Wikipedia and Gaikwad, U.S. Patent Application Publication No. 2005/0185738.
Referring to claim 21, Nakamura, as modified, has taught the device of claim 1, but has not taught wherein the swizzler circuit is configured to interleave a deinterleaved first half of a first data word with a deinterleaved second half of the first data word and to interleave a deinterleaved first half of a second data word with a deinterleaved second half of the second data word. However, Gaikwad has taught re-interleaving deinterleaved words for updating channel estimation in wireless communications (see the abstract, FIG.5 (136 and 142) to improve recovery of data being transmitted in a frame (paragraph [0010]). As a result, in order to improve wireless transmission, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nakamura to include wireless communication functionality such that the swizzler circuit is configured to interleave a deinterleaved first half of a first data word with a deinterleaved second half of the first data word and to interleave a deinterleaved first half of a second data word with a deinterleaved second half of the second data word. It should be noted that the interleaving in claim 21 may be entirely unrelated to the interleaving of claim 1.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura in view of Wikipedia, the examiner’s taking of Official Notice, and Gaikwad.
Claim 22 is rejected for similar reasoning as claim 21.
Response to Arguments
On page 9 of applicant’s response, applicant argues that the claims recite features that improve the functioning of the computer.
While there may be an improvement, “the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements.” (see MPEP 2106.05(a)). It is applicant’s mental process/math involving biasing/toggling/XOR (judicial exception) that causes the improvement. No claimed additional elements provide the improvement.
On page 10 of applicant’s response, applicant points out in items A-B that claims 1, 10, an 18 are allowable because they incorporate features of previous claims 16-17.
After further consideration, due to disclosure by Wikipedia, the examiner asserts that claim 1 is not allowable at this time. Additionally, the examiner asserts that the interleaving is not enabled.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Fletcher (US 4,667,337) has taught complementing a next output if it would otherwise cause more than half of the output lines to toggle with respect to a current output (abstract).
Naganawa (US 2004/0255062) has taught a comparator to compare data on the external bus line and data to be output on the internal bus line. An inverter outputs a signal obtained by inverting the data on the internal bus line when the number of changed bits exceeds half the total number of bits on the basis of an output result from the comparator (abstract).
Walker (US 6,046,943) has taught reducing noise involved in the switching of output circuits by comparing the bits of a first received data value with bits of a subsequently received second data value. If half or less than half of the first value data bits need to be switched in order to generate the second data value, the second data value is allowed to be driven on the communication bus. However, if more than half of the first value data bits must be switched to generate the second data value, the second data value is first inverted, and then allowed to be driven on the communication bus (background).
Al-Shamma et al. (US 6,400,633) has taught providing a power saving mode during reading of a memory device. A new memory content is read from the memory and, before being put at the memory output bus, is compared with the previously read memory content, which is currently on the output bus of the memory device. If the result of the comparison indicates that more than half of the memory output bits have to be toggled in order to put the new memory content on the memory output bus, the new data is inverted internally in order to reduce the number of output pins toggles. Then, the memory device sends a signal to the microprocessor or microcontroller indicating that the new data is inverted, and that the new data has to be inverted back before being put on the memory output bus (abstract, FIG.2).
Rallapalli (EP 0444774) has taught, to reduce the maximum possible switching transient, each new word (22a) to be applied to the bus (60) is compared to the word (22b) already on the bus (60), and, if the two words differ by more than half the number of bits in each word, the polarity of the bus (60) is inverted by XOR gates (240 .. 24N-1). In this way, no more than half the number of bits in each word will have to change at one time (abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
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