DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 (Figs. 1-4), Sub-Species B (Fig. 6), claims 1-6, 8, 12, 13, 15-21 and 24 in the reply filed on January 29,2026 is acknowledged. Claims 7, 14 and 23 have been withdrawn. However, after inspection, the Examiner notes that claims 13 and 24 do not belong to the elected Species and/or Sub-species. Examiner notes that the Applicant’s elected invention does not include an additional redistribution structure on the top surface of the molding structure. This feature belongs to non-elected Species 2, Figs. 9-12, item 100A. Therefore claims 13 and 24 have been withdrawn as well. Claims 7, 13, 14, 23 and 24 have been withdrawn. Claims 9-11, 22 and 25 have been cancelled by the Applicant. Claims 1-6, 8, 12 and 15-21 will be prosecuted. Action on the merits is as follows:
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8, 12, 15-21 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (Lee) (US 2019/0131221 A1) in view of Kim et al. (Kim) (US 2019/0189579 A1).
In regards to claim 1, Lee (Figs. 9-18B and associated text and items) discloses a semiconductor package (Fig. 17, item 100A) comprising: a redistribution structure (item 120) having a first surface (top surface of item 120) and a second surface (bottom surface of item 120) opposite to the first surface (top surface of item 120), wherein the redistribution structure (item 120) comprises a plurality of redistribution layers (item 122), the plurality of redistribution layers (item 122) including a first redistribution layer (uppermost item 122) on a first level adjacent to the first surface (top surface item 120), and a second redistribution layer (lower item 122 on item 140) on a second level adjacent to the second surface (bottom surface item 120); a semiconductor chip (items 111, 112 or 113) disposed on the first surface of the redistribution structure (item 120), wherein the semiconductor chip (items 111, 112 or 113) comprises a contact pad (items 111P, 112P or 113P) connected to the first redistribution layer (uppermost item 122), and wherein the semiconductor chip (items 111, 112 or 113) is stacked on the first surface (top surface of item 120) of the redistribution structure (item 120) along a thickness direction of the redistribution structure (item 120); and underbump metallization (UBM) layers (item 140) disposed on the second surface (bottom surface item 120) of the redistribution structure (item 120), each of the UBM layers (item 140) having a plurality of UBM vias (items 143a, 143b, 143c, 143d) connected to the second redistribution layer (lower item 122), wherein the UBM layers (item 140) include at least one UBM layer (item 140) overlapping, along the thickness direction, and the first redistribution via (item 123) is disposed so as not to overlap, along the thickness direction, the plurality of UBM vias (items 143a, 143b, 143c, 143d) of the at least one UBM layer (item 140) and to overlap, along the thickness direction, an internal region closer to a central point of the at least one UBM layer (item 140) than the plurality of UBM vias (items 143a, 143b, 143c, 143d).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of various embodiments of Lee for the purpose of various device/package structures.
Lee does not specifically disclose a frame disposed on the first surface of the redistribution structure, having a cavity accommodating the semiconductor chip therein, wherein the frame comprises a wiring structure connected to a first redistribution via of the first redistribution layer; a molding portion disposed on the first surface of the redistribution structure and encapsulating the semiconductor chip and the frame; the first redistribution via connected to the wiring structure in the thickness direction.
Kim (Figs . 9, 17 and associated text) discloses a frame (item 110) disposed on the first surface of the redistribution structure (item 140 or 145), having a cavity (item 110H) accommodating the semiconductor chip (item 120) therein, wherein the frame (item 110) comprises a wiring structure (items 112a-112d, 113a-113c) connected to a first redistribution via (item 143) of the first redistribution layer (item 145); a molding portion (item 130) disposed on the first surface of the redistribution structure (item 145) and encapsulating the semiconductor chip (item 120) and the frame (item 110); the first redistribution via (item 143) connected to the wiring structure (items 112a-112d, 113a-113c) in the thickness direction.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kim or the purpose of support, protection and an electrical connection.
In regards to claim 2, Lee (Figs. 9-18B and associated text and items) as modified by Kim (claims 2, 12, 14, Figs. 17, 9, 10) discloses wherein the at least one UBM layer (item 140, Lee) is disposed to be adjacent to each edge of the second surface of the redistribution structure (item 120, Lee, item 145, Kim).
In regards to claim 3, Lee (Figs. 9-18B and associated text and items) as modified by Kim (claims 2, 12, 14, Figs. 17, 9, 10) discloses wherein the internal region is a region surrounded at a distance of a percentage of a width of the at least one UBM layer (item 140) from the central point of the at least one UBM layer (item 140), but does not specifically disclose wherein the internal region is a region surrounded at a distance of 25% of a width of the at least one UBM layer (item 140) from the central point of the at least one UBM layer (item 140).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include an internal region being a region surrounded at a distance of 25% of a width of the at least one UBM layer from the central point of the at least one UBM layer, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 4, Lee (Figs. 9-18B and associated text and items) as modified by Kim (claims 2, 12, 14, Figs. 17, 9, 10) does not specifically disclose wherein the internal region is a region within 50 μm from the central point of the at least one UBM layer (item 140, Lee).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include an internal region being a region within 50 μm from the central point of the at least one UBM layer, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 5, Lee (Figs. 9-18B and associated text and items) as modified by Kim discloses wherein the first redistribution via (item 123) is disposed to overlap, along the thickness direction, the central point of the at least one UBM layer (item 140). Examiner takes the position that this could also be seen if the first redistribution via (item 123) was provided in the topographical views provided by Lee (Fig. 18A).
In regards to claim 6, Lee (Figs. 9-18B and associated text and items) as modified by Kim discloses wherein the at least one UBM layer (item 140) includes a plurality of UBM layers (item 140) disposed to be adjacent to each edge of the second surface (bottom surface of item 120) of the redistribution structure (item 120).
In regards to claim 8, Lee (Figs. 9-18B and associated text and items) as modified by Kim discloses wherein the plurality of UBM vias (items 143a, 143b, 143c, 143d) includes three or more UBM vias (items 143a, 143b, 143c, 143d), and the first redistribution via (item 123) is disposed to overlap, along the thickness direction, a region surrounded by the three or more UBM vias (items 143a, 143b, 143c, 143d).
In regards to claim 12, Lee (Figs. 9-18B and associated text and items) as modified by Kim discloses wherein the plurality of redistribution layers (item 122) further include at least one third redistribution layer (item 122) disposed between the first redistribution layer (uppermost item 122) and the second redistribution layer (lower item 122 on 140).
In regards to claim 15, Lee (Figs. 9-18B and associated text and items) discloses a semiconductor package (Fig. 17, item 100A) comprising: a redistribution structure (item 120) having a first surface (top surface of item 120) and a second surface (bottom surface item 120) opposite to each other, wherein the redistribution structure (item 120) comprises a plurality of redistribution layers (item 122), respectively having redistribution vias (item 123), the plurality of redistribution layers (item 122) including a first redistribution layer (uppermost item 122) on a first level adjacent to the first surface (top surface of item 120) and a second redistribution layer (lower item 122 on item 140) on a second level adjacent to the second surface (bottom surface of item 120); a semiconductor chip (items 111, 112 or 113) disposed on the first surface of the redistribution structure (item 120), wherein the semiconductor chip (items 111, 112 or 113) comprises a contact pad (items 111P, 112P or 113P) connected to the first redistribution layer (uppermost item 122), and wherein the semiconductor chip (items 111, 112 or 113) is stacked on the first surface (top surface of item 120) of the redistribution structure (item 120) along a thickness direction of the redistribution structure (item 120); and underbump metallization (UBM) layers (item 140) disposed on the second surface of the redistribution structure (item 120), each of the UBM layers (item 140) having a plurality of UBM vias (items 143a-143d) connected to the second redistribution layer (lower item 122), wherein the UBM layers (item 140) include at least one UBM layer (item 140) overlapping the first redistribution via (item 123) in the thickness direction of the redistribution structure (item 120), and the first redistribution via (item 123) is disposed so as not to overlap, along the thickness direction, the plurality of UBM vias (items 143a-143d) of the at least UBM layer (item 140) and to overlap, along the thickness direction, an internal region closer to a central point of the at least one UBM layer (item 140) than the plurality of UBM vias (items 143a-143d).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of various embodiments of Lee for the purpose of various device/package structures.
Lee does not specifically disclose a vertical connection conductor disposed around the semiconductor chip on the first surface of the redistribution structure, wherein the vertical connection conductor is connected to the first redistribution layer, the first redistribution layer having a first redistribution via overlapping, along the thickness direction, the vertical connection conductor; a molding portion disposed on the first surface of the redistribution structure, wherein the molding portion encapsulates the semiconductor chip and the vertical connection conductor.
Kim (Figs . 9, 17 and associated text) discloses a vertical connection conductor (items 112a-112d, 113a-113c) disposed around the semiconductor chip (item 120) on the first surface of the redistribution structure (item 145), wherein the vertical connection conductor (items 112a-112d, 113a-113c) is connected to the first redistribution layer (item 145), the first redistribution layer (item 145) having a first redistribution via (item 143) overlapping, along the thickness direction, the vertical connection conductor (items 112a-112d, 113a-113c); a molding portion (item 130) disposed on the first surface of the redistribution structure (item 145), wherein the molding portion (item 130) encapsulates the semiconductor chip (item 120) and the vertical connection conductor (items 112a-112d, 113a-113c).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kim or the purpose of protection and an electrical connection.
In regards to claim 16, Lee (Figs. 9-18B and associated text and items) as modified by Kim (Figs . 9, 17 and associated text) discloses wherein the redistribution vias (item 123, Lee, item 143, Kim) extend toward the first surface of the redistribution structure (item 120, item 145) on an upper surface of each of the plurality of redistribution layers (items 122, Lee, item 145), and the first redistribution via (item 123, Lee, item 143, Kim) is connected to a lower surface of the vertical connection conductor (items 112a-112d, 113a-113c).
In regards to claim 17, Lee (Figs. 9-18B and associated text and items) as modified by Kim (Figs . 9, 17 and associated text) discloses wherein the redistribution vias (item 123, Lee, item 143, Kim) extend toward the second surface of the redistribution structure (item 120, Lee, item 140 or 145, Kim) on a lower surface of each of the plurality of redistribution layers (item 122, Lee, item 145, Kim), the vertical connection conductor (items 112a-112d, 113a-113c) is connected to an upper surface of the first redistribution layer layers (item 122, Lee, item 145, Kim), and the plurality of redistribution layers (item 122, Lee, item 145, Kim) further include a redistribution pattern layer (item 122, Lee, item 145, Kim) disposed between the second redistribution layer (lower item 122, Lee) and the UBM layer (item 145, Lee, item 160, Kim) and connected to the plurality of UBM vias (items 143a-143d, Kim).
In regards to claim 18, Lee (Figs. 9-18B and associated text and items) as modified by Kim (claims 2, 12, 14, Figs. 17, 9, 10) discloses wherein the internal region is a region surrounded at a distance of a percentage of a width of the at least one UBM layer (item 140) from the central point of the at least one UBM layer (item 140), but does not specifically disclose wherein the internal region is a region surrounded at a distance of 25% of a width of the at least one UBM layer (item 140) from the central point of the at least one UBM layer (item 140).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include an internal region being a region surrounded at a distance of 25% of a width of the at least one UBM layer from the central point of the at least one UBM layer, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 19, Lee (Figs. 9-18B and associated text and items) as modified by Kim (claims 2, 12, 14, Figs. 17, 9, 10) discloses wherein the plurality of UBM vias (items 143a-143d) include four UBM vias (items 143a-143d) arranged in a square, and the first redistribution via (items 123, Lee) is disposed to overlap, along the thickness direction, a region from the central point of the at least one UBM layer (item 140, Lee), but does not specifically disclose the first redistribution via (items 123, Lee) is disposed to overlap, along the thickness direction, a region within 50 μm from the central point of the at least one UBM layer (item 140, Lee).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include an internal region being a region within 50 μm from the central point of the at least one UBM layer, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 20, Lee (Figs. 9-18B and associated text and items) discloses a semiconductor package (Fig. 17, item 100A) comprising: a redistribution structure (item 120) having a first surface (top surface of item 120) and a second surface (bottom surface of item 120) opposite to each other, wherein the redistribution structure (item 120) comprises a plurality of redistribution layers (item 122) disposed on different levels and respectively having redistribution vias (item 123) formed to face the first surface (top surface item 120), the plurality of redistribution layers (item 122) including a first redistribution layer (upper item 122) on a first level adjacent to the first surface (top surface of item 120) and a second redistribution layer (lower item 122) on a second level adjacent to the second surface (bottom surface item 120); a semiconductor chip (items 111, 112 or 113) disposed on the first surface of the redistribution structure (item 120), wherein the semiconductor chip (items 111, 112 or 113) comprises a contact pad (items 111P, 112P or 113P) connected to the first redistribution layer (upper item 122), and wherein the semiconductor chip (items 111, 112 or 113) is stacked on the first surface of the redistribution structure (item 120) along a thickness direction of the redistribution structure (item 120); and underbump metallization (UBM) layers (item 140) disposed on the second surface (bottom surface of item 120) of the redistribution structure (item 120), each of the UBM layers (item 140) having a plurality of UBM vias (items 143a-143d) connected to the second redistribution layer (lower item 122), wherein the UBM layers (item 140) include at least one UBM layer (item 140) overlapping the first redistribution via (item 123) in the thickness direction, and the first redistribution via (item 123) is disposed so as not to overlap, along the thickness direction, the plurality of UBM vias (items 143a-143d) of the at least UBM layer (item 140) and to overlap, along the thickness direction, a region from a central point of the at least one UBM layer (item 140).
Lee does not specifically disclose a vertical connection conductor disposed around the semiconductor chip on the first surface of the redistribution structure, wherein the vertical connection conductor is connected to a first redistribution via of the first redistribution layer; a molding portion disposed on the first surface of the redistribution structure, wherein the molding portion covers the semiconductor chip and the vertical connection conductor;
Kim (Figs . 9, 17 and associated text) discloses a vertical connection conductor (items 112a-112d, 113a-113c) disposed around the semiconductor chip (item 120) on the first surface of the redistribution structure (item 145), wherein the vertical connection conductor (items 112a-112d, 113a-113c) is connected to the first redistribution layer (item 145) of the first redistribution layer (item 145); a molding portion (item 130) disposed on the first surface of the redistribution structure (item 145), wherein the molding portion (item 130) covers the semiconductor chip (item 120) and the vertical connection conductor (items 112a-112d, 113a-113c).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kim or the purpose of protection and an electrical connection.
Lee as modified by Kim does not specifically disclose the first redistribution via (item 123) is disposed so as not to overlap, along the thickness direction, the plurality of UBM vias (items 143a-143d, Lee) of the at least UBM layer (item 140, Lee, item 160, Kim) and to overlap, along the thickness direction, a region within 50 μm from a central point of the at least one UBM layer (item 140, Lee, item 160, Kim).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a region within 50 μm from the central point of the at least one UBM layer, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 21, Lee (Figs. 9-18B and associated text and items) as modified by Kim (Figs . 9, 17 and associated text) discloses a frame (item 110, Kim) disposed on the first surface of the redistribution structure (item 120, Lee, item 145, Kim) and having a cavity (item 110H, Kim) accommodating the semiconductor chip (items 111, 112 or 113, Lee, item 120, Kim) therein, wherein the vertical connection conductor (items 112a-112d, 113a-113c) includes a wiring structure (items 112a-112d, 113a-113c) connecting an upper surface and a lower surface of the frame (item 110) to each other.
EXAMINER’S COMMENTS
Examiner notes that the Applicant’s claimed invention could have been rejected by Kim in view of Lee as well. See teachings from the above rejection and written search report provided by the Applicant. Examiner suggests the Applicant takes this into consideration before responding.
Conclusion
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 February 10, 2026