DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 8-13, and 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chandra, US PGPUB No. 2009/0019411.
In reference to claim 1, Chandra teaches an apparatus (Figure 4B) comprising:
programmable circuitry (Figure 4B Processor 302);
interface circuitry (Figure 4D, Paragraph [0072] user interface); and
instructions to program the programmable circuitry (Paragraph [0012]) to:
map a circuit layout to a hardware description language model of a circuit
to generate a power density map for the circuit (Figure 4A, 202a-202g, paragraph [0066] are the inputs that are used to determine the power density distribution (Paragraph [0175]) of the circuit, Paragraph [0141] Power densities of the devices and resistor elements of the interconnects);
estimate a temperature gradient of a first area of the circuit and a second area of the circuit based on the power density map (Paragraphs [0162-0174] determining local grid temperature gradients, Paragraph [0115-0116] hot region, cool region);
identify the first area as a hotspot based on the temperature gradient meeting a threshold value (Paragraph [0115-0116] hot region); and
determine a predicted timing change due to the temperature gradient (Paragraph [0116] provide STA with information describing the temperature affected relative timing performance between Cool Region and Hot Region).
In reference to claim 2, Chandra teaches wherein the programmable circuitry is to
predict a thermal response of the first area of the circuit based a thermal spreading kernel
that is process dependent, including a metal pattern on a back-side of the first area (Paragraphs [0062] and [0114]).
In reference to claim 3, Chandra teaches wherein the programmable circuitry is further
to predict the thermal response of the first area of the circuit based on a local temperature rise at a transistor layer (Paragraph [0108] transistors thermal analysis), a front-side interconnect thermal resistance (Paragraph [0086] interconnect resistance), and the power density map (Paragraph [0175] power density distribution).
In reference to claim 4, Chandra teaches wherein the instructions program the programmable circuitry to cause a compensation to be applied to the circuit to compensate
for the predicted timing change (Paragraph [0067] thermal repairs).
In reference to claim 8, Chandra teaches wherein the programmable circuitry is to
provide the power density map at more than one resolution (Paragraph [0140]-[0153] variable grid granularities).
In reference to claim 9, Chandra teaches wherein the programmable circuitry is to
adjust the resolution of the power density map based on a user input (Paragraph [0199] user controls the spatial resolution).
In reference to claims 10-13 and 17-20 drawn to computer readable media and methods containing all of the same functional limitations as found in claims 1-4, 8, and 9, the same rejections apply.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5, 6, 14, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chandra, US PGPUB No. 2009/0019411 in view of Gallina et al., US PGPUB No. 2022/0114318.
In reference to claims 5 and 6, Chandra teaches claims 1 and 4 as described above. Chandra does not teach wherein to compensate for a predicted timing change including assigning a thermal guard band to the circuit and increasing a guard band temperature range based on the threshold value being exceeded. Gallina teaches including assigning a thermal guard band to the circuit and increase a guard band temperature range based on the threshold value being exceeded (Paragraph [0017], Figure 2). Accordingly, it would have been obvious for one of ordinary skill in the art at the time of invention to incorporate including assigning a thermal guard band to the circuit and increase a guard band temperature range based on the threshold value being exceeded as taught by Gallina into the apparatus of Chandra because it would prevent the temperature from going beyond its limits, thereby preventing damage or malfunction of the circuit.
In reference to claims 14 and 15 drawn to computer readable media and methods containing all of the same functional limitations as found in claims 5 and 6, the same rejections apply.
Claim(s) 7 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chandra, US PGPUB No. 2009/0019411 in view of Palisetti et al., US PGPUB No. 2011/0218779.
In reference to claim 7, Chandra teaches claim 1 as described above. Chandra does not teach determining a per-cell power prediction based on a register transfer level description of the circuit. Palisetti teaches determining a per-cell power prediction based on a register transfer level description of the circuit (Paragraph [0017]). Accordingly, it would have been obvious for one of ordinary skill in the art at the time of invention to incorporate determining a per-cell power prediction based on a register transfer level description of the circuit into the apparatus of Chandra because it would optimize power performance for the circuit by maximizing a weighted activity metric that is defined in terms of capacitance, switching activity and power effort
In reference to claim 16 drawn to computer readable media and methods containing all of the same functional limitations as found in claim 7 the same rejections apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON BOWERS whose telephone number is (571)272-1888. The examiner can normally be reached Flex M-F 7am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.B/Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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