DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-19 in the reply filed on 11 December 2025 is acknowledged. Claim 21 is newly added.
Specification
The disclosure is objected to because of the following informalities:
[0018]The present disclosure provides novel techniques to address the above-mentioned problems. In one or more embodiments, by forming a dielectric gate isolation section (i.e., a section composed of a dielectric material in a gate structure), parasitic capacitance is reduced between the dielectric gate isolation section and a conductive element adjacent to or nearby the dielectric gate isolation section. As a result, a semiconductor device with increased operation speed and/or reduced power consumption compared to the other approaches is obtainable. In addition, the dielectric gate isolation sections may also prevent or reduce the gate-to-drain leakage, which is usually generated by the conventional gate isolation section composed of a conductive material. The dielectric gate isolation sections according to the present disclosure may be formed by using original CPO pattern used in the fabrication process without additional patterning. In at least one embodiment, one or more of the described effects, such as circuit density, performance and power consumption improvements, are achievable without extra cost and/or area penalty.
[0032]The constituent material of the gate isolation section is different from the gate electrode(s) on the same gate structure. For example, the gate isolation section 151 of the CPO 155 includes polysilicon. In other words, the gate isolation section 151 functions as a conventional dummy gate section that logically isolates the gate electrode 181 from other sections in the gate structure 121. In contrast, the gate isolation sections 152 and 153 of the CPO 156 include a dielectric material, such as SiN, which is substantially less conductive than polysilicon or metal. Due to the dielectric property, the parasitic capacitance between the gate isolation section 152 and the adjacent metal contact 143 (i.e., in the region 159), as well as the parasitic capacitance between the gate isolation section 153 and the adjacent metal contact 143 (i.e., in the region 160) can be significantly reduced, as compared with the gate isolation section composed of polysilicon or metal. In other words, the gate isolation sections 152 and 153 composed of a dielectric material not only functions as a dummy gate section to logically isolate gate electrodes but also prevents formation of parasitic capacitor (e.g., in the regions 159 and 160). Accordingly, the gate isolation sections 152 and 153 can reduce or minimize the parasitic capacitance between the gate isolation section and the adjacent metal contact and/or prevent gate-to-drain leakage. As such, the performance of the FinFETs 166, 167, 169, and 170 in proximity to the gate isolation sections 152 and 153 can be improved.
Appropriate correction is required.
Claim Objections
Claim 1 is objected to because of the following informalities:
1. (Original) A semiconductor device, comprising: …
wherein the at least one gate structure further comprises:
at least one gate electrode coupled to the at least one fin;…
at least one metal contact formed on the at least one fin extending along the second horizontal direction and adjacent to the at least one gate structure;
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ha et al. US 2023/0053251.
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Ha et al. US 2023/0053251
Regarding claim 1, Ha et al. in Figs. 1A-1B discloses a semiconductor device, comprising:
a substrate 101;
at least one fin F1 formed on the substrate 101, the at least one fin F1 extending along a first horizontal direction;
at least one gate structure GLB formed on the at least one fin F1 and extending along a second horizontal direction, the second horizontal direction being substantially perpendicular to the first horizontal direction; and
at least one metal contact CA1 formed on the at least one fin F1 extending along the second horizontal direction and adjacent to the gate structure GLB;
wherein the at least one gate structure GLB further comprises:
at least one gate electrode 115b coupled to the at least fin; and
at least one dielectric gate isolation section SDB separated from the at least one gate electrode 115b, the at least one dielectric gate isolation section comprising a dielectric material [0023];
wherein a portion of the dielectric gate isolation section SDB is aligned with a portion of the metal contact CA1 adjacent and proximate to the dielectric gate isolation section SDB in the first horizontal direction.
Regarding claim 2, Ha et al. in Figs. 1A-1B discloses the semiconductor device of claim 1, further comprising:
a gate spacer 114 disposed on one side of the gate structure GLB, wherein at least a portion of the gate spacer 114 is disposed between the dielectric gate isolation section SDB and the adjacent metal contact CA1.
Regarding claim 3, Ha et al. in Figs. 1A-1B discloses the semiconductor device of claim 1, wherein two source/drain regions 120 are formed respectively on two sides of the gate electrode 115b, and wherein the gate electrode 115b and the two source/drain regions 120 form a fin field effect transistor (FinFET).
Regarding claim 4, Ha et al. in Figs. 1A-1B discloses the semiconductor device of claim 1, wherein the gate electrode 115b further comprises:
a gate dielectric layer 116b in contact with the fin F1; and a gate metal layer [0028] disposed on the gate dielectric layer 116b.
Regarding claim 5, Ha et al. in Figs. 1A-1B discloses the semiconductor device of claim 1, wherein the dielectric material of the dielectric gate isolation section SDB is silicon nitride (SiN) [0023].
Regarding claim 7, Ha et al. in Figs. 1A-1B discloses the semiconductor device of claim 1, wherein the dielectric gate isolation section SDB extends in a full width of the gate structure GLB along the first horizontal direction.
Regarding claim 8, Ha et al. in Figs. 1A-1B discloses the semiconductor device of claim 1, further comprising at least one via contact V1 disposed on the gate electrode or the metal contact CA1.
Claim(s) 9-11, 17-19 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liaw US 2022/0367659.
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Liaw US 2022/0367659
Regarding claim 9, Liaw in Figs. 1, 3 (annotated above) discloses a semiconductor device comprising:
a substrate 202;
a first active region 204B and a second active region 204A formed over the substrate 202;
a first fin and a second fin respectively 205B/205A formed in the first and second active regions, the first and second fins extending along a first horizontal direction;
a first gate structure 240 formed on the first and second fins and extending along a second horizontal direction across a boundary between the first and second active regions, the second horizontal direction being substantially perpendicular to the first horizontal direction; and
a first metal contact CONTACT formed on the first and second fins and extending along the second horizontal direction across the boundary between the first and second active regions, wherein the first gate structure 240 is adjacent to a first side of the first metal contact;
wherein the first gate structure 240 further comprises:
a first gate electrode 350 and a second gate electrode 350 respectively coupled to the first and second fins; and
a first gate isolation section 404 between the first and second gate electrodes, wherein the first gate isolation section 404 isolates and interconnects the first and second gate electrodes 350, and the first gate isolation section 404 comprises a first material, the first material being a dielectric material [0035]-[0036],
wherein a portion of the first gate isolation section 404 is adjacent and proximate to the first side of the first metal contact and aligned with a portion of the first metal contact in the first horizontal direction.
Regarding claim 10, Liaw in Figs. 1, 3 (annotated above) discloses the semiconductor device of claim 9, wherein the dielectric material is SiN [0036].
Regarding claim 11, Liaw in Figs. 1, 3 (annotated above) discloses the semiconductor device of claim 9, wherein the first gate isolation section 404 extends across the boundary between the first and second active regions 204B/204A.
Regarding claim 17, Liaw in Figs. 1, 3 (annotated above) discloses the semiconductor device of claim 9, further comprising:
a third gate structure 240 formed on the second fin and extending in the second horizontal direction; and
a second metal contact CONTACT formed on the second fin and extending in the second horizontal direction, the second metal contact being adjacent to the third gate structure 240, wherein the third gate structure further comprises:
a fifth gate electrode 350 coupled to the second fin; and
a third gate isolation section 404 comprising a third material;
wherein a portion of the third gate isolation section 404 is adjacent and proximate to a side of the second metal contact and aligned with a portion of the second metal contact in the first horizontal direction.
Regarding claim 18, Liaw in Figs. 1, 3 (annotated above) discloses semiconductor device of claim 17, wherein the third material is the same as the first material [0035]-[0036].
Regarding claim 19, Liaw in Figs. 1, 3 (annotated above) discloses semiconductor device of claim 17, wherein the third material is a conductive material [0035]-[0036].
Regarding claim 21, Liaw in Figs. 1, 3 (annotated above) discloses a semiconductor device, comprising:
a substrate 202;
a fin extending 205B/205A from the substrate along a first direction;
a gate structure 240 disposed over the fin and extending along a second direction perpendicular to the first direction, the gate structure comprising a gate electrode 350 containing a work function metal [0033] and a dielectric isolation section 404; and
a contact structure CONTACT extending along the second direction and adjacent to the gate structure;
wherein the dielectric isolation section 404 separates the gate electrode from a second portion of the gate structure;
wherein the dielectric isolation section 404 is composed of silicon nitride (SiN) and is aligned with the contact structure in the first direction to reduce parasitic capacitance between the gate structure and the contact structure [0035]-[0036].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ha et al.
Regarding claim 6, Ha et al. in Figs. 1A-1B discloses the semiconductor device of claim 1 but does not expressly disclose wherein the dielectric gate isolation section has a length in the second horizontal direction from 16 nm to 100 nm.
Applicant has not disclosed that having the dielectric gate isolation section having a length in the second horizontal direction from 16 nm to 100 nm, solves any stated problem or is for any particular purpose.
However, Ha et al. in [0083]-[0085] teaches that the width of the dielectric gate isolation region SDB varies and the performance of the PMOS and NMOS region are improved using different structures and/or different types of diffusion break regions. Furthermore, the gate line of the NMOs region can be prevented from being lost using a gate isolation layer so that the cause of deterioration of characteristics of a transistor can be fundamentally eliminated. This demonstrates that to improve the performance device, from which the dimensions of the SDB depends, the SDB would be considered a result effective variable.
Accordingly, the claim is obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would recognize that it would be obvious to adjust the dielectric gate isolation section in order to improve the device performance thereof and optimize “the length of the dielectric gate isolation section in the second horizontal direction from 16 nm to 100 nm” as a “result effective variable”, and arrives at the recited limitation.
Allowable Subject Matter
Claims 12-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
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/Sonya McCall-Shepard/Primary Examiner, Art Unit 2898