DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Applicant’s amendment of claims 1, 3-4 and 21, and cancellation of claim 20 in “Claims - 05/12/2026” is acknowledged.
This office action considers claims 1-19 and 21 are pending for prosecution, of which, claims 1-19 and 21 are presented for further examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:uu
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, (100a; Fig 1A; [0015]) = (element 100a; Figure No. 1A; Paragraph No. [0015]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1, 21 and 2-8 are rejected under 35 U.S.C. 103 as being unpatentable over HA; Seung Seok et al., (US 20230053251 A1) hereinafter represented as Ha’251) in view of Chang; Che-Cheng et al., (US 20140120722 A1; hereinafter represented as Chang).
Regarding claim 1, Ha’251 teaches a semiconductor device (100a; Figs 1A-1D; [0015]), comprising (see the entire document, figs 1A-1D along with other relevant figures and associated description, specifically, as cited below):
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Ha’251 Figure 1A Figure 1B
a substrate (101; 1B; [0015]);
at least one fin (F1; [0015]) formed on the substrate (101), the at least one fin (F1) extending along a first horizontal direction;
at least one gate structure (GLB) formed on the at least one fin (F1) and extending along a second horizontal direction, the second horizontal direction being substantially perpendicular to the first horizontal direction; and
at least one metal contact (CA1) formed on the at least one fin (F1) extending along the second horizontal direction and adjacent to the at least one gate structure (GLB);
wherein the at least one gate structure (GLB/GL) further comprises:
a first gate electrode (115) and a second gate electrode (115b), wherein at least one of the first gate electrode and the second gate electrode is coupled to the at least one fin; and
But, Ha’251 does not expressly disclose:
“at least one dielectric gate isolation section disposed between and contacting the first gate electrode (GL) and the second gate electrode (GBL), the at least one dielectric gate isolation section comprising a dielectric material;
wherein a portion of the dielectric gate isolation section is aligned with a portion of the metal contact (CA1) adjacent and proximate to the dielectric gate isolation section in the first horizontal direction.
However, in the analogous art, Chang teaches Structures and formation methods of a semiconductor device structure (110A,110B; Fig 1i) that includes a fin structure over a semiconductor substrate, a gate stack covering a portion of the fin structure (101A,101B) and an isolation element (134’) over the semiconductor substrate (100) and adjacent to the gate stack (Abstract, [0056,0070]), , wherein (Fig 1i; [0070]) a dielectric gate isolation section (134’; Fig 1i; [0070]disposed between and contacting the first gate electrode (133A) and the second gate electrode (133B), the at least one dielectric gate isolation section (134’) comprising a dielectric material (0049]);
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Ha’251’s structure by contemplating Chang’s dielectric gate isolation section (134’ and thereafter The combination of (Ha’251 and Chang) comprises “at least one dielectric gate isolation section (Chang’s 134’) disposed between and contacting the first gate electrode and the second gate electrode (GLB/GL), the at least one dielectric gate isolation section comprising a dielectric material (Chang [0049]) since this this inclusion, at least, helps electrically separate neighboring gate stacks (Chang [0071]).
The combination of (Ha’251 and Chang) further teaches wherein a portion of the dielectric gate isolation section ( Chang 134) is aligned with a portion of the metal contact (CA1) adjacent and proximate to the dielectric gate isolation section ( Chang 134) in the first horizontal direction.
Regarding claim 21, Ha’251 teaches a semiconductor device (100a; Figs 1A-1D; [0015]), comprising (see the entire document, figs 1A-1D along with other relevant figures and associated description, specifically, as cited below):
a substrate (101; 1B; [0015]);
a fin (F1; [0015]) extending from the substrate (101) along a first direction;
a gate structure (GLB/GL) disposed over the fin (F1) and extending along a second direction perpendicular to the first direction, the gate structure comprising a first gate electrode ((115) containing a work function metal ([0028]) , a second gate electrode (115b), and
a first gate electrode (115) and a second gate electrode (115b), wherein at least one of the first gate electrode and the second gate electrode is coupled to the at least one fin; and wherein at least one of the first gate electrode and the second gate electrode couple to the fin (F1); and
a contact structure (CA1) extending along the second direction and adjacent to the gate structure (GLB/GL);
But, Ha’251 does not expressly disclose:
a dielectric isolation section, wherein the dielectric isolation section separates and contacts the firs gate electrode (115) and the second gate electrode (115b) from a second portion of the gate structure; wherein the dielectric isolation section is composed of silicon nitride (SiN) and
is aligned with the contact structure in the first direction to reduce parasitic capacitance between the gate structure and the contact structure
However, in the analogous art, Chang teaches Structures and formation methods of a semiconductor device structure (110A,110B; Fig 1i) that includes a fin structure over a semiconductor substrate, a gate stack covering a portion of the fin structure (101A,101B) and an isolation element (134’) over the semiconductor substrate (100) and adjacent to the gate stack (Abstract, [0056,0070]), , wherein (Fig 1i; [0070]) a dielectric gate isolation section (134’; Fig 1i; [0070]disposed between and contacting the first gate electrode (133A) and the second gate electrode (133B), wherein the dielectric isolation section (Chang’s 134’) is composed of silicon nitride (SiN) [0049]
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Ha’251’s structure by contemplating Chang’s dielectric gate isolation section (134’ and thereafter The combination of (Ha’251 and Chang) comprises “
a dielectric isolation section (Chang’s 134’), wherein the dielectric isolation section separates and contacts the firs gate electrode (115) and the second gate electrode (115b) from a second portion of the gate structure; wherein the dielectric isolation section (Chang’s 134’) is composed of silicon nitride (SiN) ((Chang’ [0049)), since this this inclusion, at least, helps electrically separate neighboring gate stacks (Chang [0071]).
The combination of (Ha’251 and Chang) further teaches
wherein the dielectric isolation section ( Chang 134) is aligned with the contact structure (CA1) in the first direction to reduce parasitic capacitance between the gate structure and the contact structure.
Regarding claim 2, The combination of (Ha’251 and Chang) as applied to the semiconductor device of claim 1, Ha’251 further teaches, (the device) further comprising:
a gate spacer (114) disposed on one side of the gate structure (GLB), wherein at least a portion of the gate spacer is disposed between the dielectric gate isolation section (Chang’s 134’) and the adjacent metal contact (CA1).
Regarding claim 3, The combination of (Ha’251 and Chang) as applied to the semiconductor device of claim 1, Ha’251 further teaches, wherein two source/drain regions (120) are formed respectively on two sides of the first gate electrode (115), and wherein the first gate electrode (115) and the two source/drain regions (120) form a fin field effect transistor (FinFET).
Regarding claim 4, The combination of (Ha’251 and Chang) as applied to the semiconductor device of claim 1, Ha’251 further teaches, wherein the first gate electrode (115) further comprises:
a first gate dielectric layer (116; [0028]) in contact with the fin (F1); and a gate metal layer [0028] disposed on the gate dielectric layer (116).
Regarding claim 5, The combination of (Ha’251 and Chang) as applied to the semiconductor device of claim 1, Ha’251 further teaches, wherein the dielectric material of the dielectric gate isolation section (Chang’s 134’) is silicon nitride (SiN) [0049].
Regarding claim 6, The combination of (Ha’251 and Chang) as applied to the semiconductor device of claim 1, further teaches, wherein the dielectric gate isolation section (Chang 134’) has a length in the second horizontal direction from 16 nm to 100 nm (Chang [0053]: W2 is 10 nm to 500 nm; some of which overlaps claimed range of 16 nm to 100).
However, In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. See MPEP 2144.05, I. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to enable using the length range disclosed in the prior art of record to arrive at the recited limitation.
Regarding claim 7, The combination of (Ha’251 and Chang) as applied to the semiconductor device of claim 1, Ha’251 further teaches,, wherein the dielectric gate isolation section (Chang’s 134’) extends in a full width of the gate structure (GLB) along the first horizontal direction.
Regarding claim 8, The combination of (Ha’251 and Chang) as applied to the semiconductor device of claim 1, Ha’251 further teaches, (the device) further comprising at least one via contact (V1) disposed on the gate electrode or the metal contact (CA1).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9-11, and 17-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liaw (US 2022/0367659 A1) hereinafter represented as Liaw.
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Liaw US 2022/0367659
Regarding claim 9, Liaw in Figs. 1, 3 (annotated above) discloses a semiconductor device comprising:
a substrate 202;
a first active region 204B and a second active region 204A formed over the substrate 202;
a first fin and a second fin respectively 205B/205A formed in the first and second active regions, the first and second fins extending along a first horizontal direction;
a first gate structure 240 formed on the first and second fins and extending along a second horizontal direction across a boundary between the first and second active regions, the second horizontal direction being substantially perpendicular to the first horizontal direction; and
a first metal contact CONTACT formed on the first and second fins and extending along the second horizontal direction across the boundary between the first and second active regions, wherein the first gate structure 240 is adjacent to a first side of the first metal contact;
wherein the first gate structure 240 further comprises:
a first gate electrode 350 and a second gate electrode 350 respectively coupled to the first and second fins; and
a first gate isolation section 404 between the first and second gate electrodes, wherein the first gate isolation section 404 isolates and interconnects the first and second gate electrodes 350, and the first gate isolation section 404 comprises a first material, the first material being a dielectric material [0035]-[0036],
wherein a portion of the first gate isolation section 404 is adjacent and proximate to the first side of the first metal contact and aligned with a portion of the first metal contact in the first horizontal direction.
Regarding claim 10, Liaw in Figs. 1, 3 (annotated above) discloses the semiconductor device of claim 9, wherein the dielectric material is SiN [0036].
Regarding claim 11, Liaw in Figs. 1, 3 (annotated above) discloses the semiconductor device of claim 9, wherein the first gate isolation section 404 extends across the boundary between the first and second active regions 204B/204A.
Regarding claim 17, Liaw in Figs. 1, 3 (annotated above) discloses the semiconductor device of claim 9, further comprising:
a third gate structure 240 formed on the second fin and extending in the second horizontal direction; and
a second metal contact CONTACT formed on the second fin and extending in the second horizontal direction, the second metal contact being adjacent to the third gate structure 240, wherein the third gate structure further comprises:
a fifth gate electrode 350 coupled to the second fin; and
a third gate isolation section 404 comprising a third material;
wherein a portion of the third gate isolation section 404 is adjacent and proximate to a side of the second metal contact and aligned with a portion of the second metal contact in the first horizontal direction.
Regarding claim 18, Liaw in Figs. 1, 3 (annotated above) discloses semiconductor device of claim 17, wherein the third material is the same as the first material [0035]-[0036].
Regarding claim 19, Liaw in Figs. 1, 3 (annotated above) discloses semiconductor device of claim 17, wherein the third material is a conductive material [0035]-[0036].
Allowable Subject Matter
Claims 12-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments “Remarks - 05/12/2026 - Applicant Arguments/Remarks Made in an Amendment, have been fully considered, but they are not persuasive because of the following:
Applicant’s amendment of independent claims 1 and 21 in “Claims - 05/12/2026” changed scope of the inventions significantly, and necessitated the shift in new grounds of rejection detailed in sections i, supra. The shift in grounds of rejection renders Applicant’s arguments moot.
This office action maintains the rejection of claims 9-11, and 17-19 and indication of claim objection of claims 12-16 in the Non-Final Rejection - 01/13/2026. Please note that Applicant's arguments for 9-11, and 17-19 are not persuasive, for more clarification subject matter of new claims rejection cited in section I, supra can be used as MPEP § 2141.02. VI suggests that “prior arts reference must be considered in its entirety, i.e., as a whole, W.L. Gore & Associates, Inc. v. Garlock, Inc., 721 F.2d 1540, 220 USPQ 303 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moazzam Hossain whose telephone number is (571)270-7960. The examiner can normally be reached on Mon to Friday 8.30 A.M -5.00 P.M.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
September 9, 2026
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