DETAILED ACTION
Claims 1, 4-13, 15-23 are pending. Claim(s) 2-3, 14 are cancelled. Claims 22-23 are new.
Priority: 6/30/2023
Assignee: Xilinx
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim(s) 4, 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 21 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim(s) 21 recites the limitation "the second set" in the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5, 7, 8, 9, 11, 12, 13, 16, 17, 19, 20, 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kanno(20170262175).
As per claim 1, Kanno discloses:
A computer-implemented method for memory management, the computer-implemented method being performed by a computing device comprising at least one circuit(Kanno, [0087 -- The controller 4 is electrically connected to the NAND memory 5 as a nonvolatile memory through a NAND interface 13, such as a toggle or ONFI. The controller 14 may have a physical resources management function for managing the physical resources of the SSD 3, namely, the NAND memory. ]), the computer-implemented method comprising:
storing a content in a physical memory(Kanno, [0270 -- When the host 2 wants to access the SSD 3 using the physical NAND access management API 21, it may request the SSD 3 to allocate one block. This request may be the above-mentioned block allocate and erase command.]), the storing comprising:
generating a buffer of a set of one or more memory blocks of virtual memory(Kanno, [0133 -- When the host 2 has requested the SSD 3 to allocate one virtual block, the block allocate and erase control unit 25 may allocate one virtual block in the free virtual blocks for the host 2]), wherein the buffer of the set of one or more memory blocks of virtual memory is allocated for storing the content into one or more of a plurality of memory banks that subdivide the physical memory(Kanno, [0133 -- Afterward, the host 2 can access the allocated virtual block (for read, write and/or erase operation) using the informed physical address.], [0273 -- The host 2 transmits, to the SSD 3, a read, write or erase command including the notified virtual block address. Upon reception of the read, write or erase command including the virtual block address, namely, a read, write or erase command for the virtual NAND access management API 22, the controller 4 performs a read, write or erase operation on a set of blocks included in a specific virtual block designated by the virtual block address (step S12)], [0330 -- Upon receiving the block allocate and erase command from the host 2, the controller 4 of the SSD 3 selects one virtual block from the free virtual block list 72B, and allocates, for the host 2, the selected virtual block as a write target virtual block (step S21).]);
assigning an identifier to the set of one or more memory blocks of the virtual memory that store the content to link the set of one or more memory blocks together in the buffer(Kanno, [0237 -- In this case, for example, the combinations of the block addresses of a plurality of blocks belonging to a virtual block having virtual block address VB0 are determined as block address 0 of channel Ch.A, block address 100 of channel Ch.B, block address 0 of channel Ch.C and block address 100 of channel Ch.D]);
and outputting the identifier for the set of one or more memory blocks of the virtual memory, the identifier to be used to access the set of one or more memory blocks where the content is stored(Kanno, [0133 -- inform the host 2 of a physical address (virtual block address) that designates the allocated virtual block], [0316 -- Block address: The virtual block address of an allocated virtual block is returned to the host 2.], [0327 -- The controller 4 notifies the host 2 of the block address of this allocated block (step S23). The host 2 may be notified of this block address as a return value included in a command completion response to the block allocate and erase command.]);
As per claim 5, the rejection of claim 1 is incorporated, in addition, Kanno discloses:
assigning a respective identifier to each of one or more sets of one or more memory blocks of the virtual memory that store the content(Kanno, [0237 -- FIG. 13 shows an example case of using a mathematical rule that block addresses 0 to 100 associated with channel Ch.A are allocated in ascending order to virtual block addresses VB0 to VB100, block addresses 0 to 100 associated with channel Ch.B are allocated in descending order to virtual block addresses VB0 to VB100, block addresses 0 to 100]).
As per claim 7, the rejection of claim 5 is incorporated, in addition, Kanno discloses:
assigning each block of the one or more sets of one or more memory blocks to a respective memory bank of the plurality of memory banks(Kanno, [0094 -- The physical address corresponding to a certain LBA indicates a location in the NAND memory 5 in which data corresponding to this certain LBA is stored (i.e., a physical storage location). ]);
receiving one or more requests for one or more identifiers of the one or more sets of one or more memory blocks of the virtual memory(Kanno, [0271 -- When the host 2 wants to access the SSD 3 using the virtual NAND access management API 22, it may request the SSD 3 to allocate one virtual block.]);
and outputting, responsive receiving the one or more requests, the one or more identifiers in an order based on the number of identifiers associated with each of the plurality of memory banks(Kanno, [0271 -- a virtual block (a currently unused virtual block) which does not include valid data, allocates the selected virtual block for the host 2, and notifies the host 2 of the physical address (virtual block address) of this allocated virtual block.]).
As per claim 8, the rejection of claim 5 is incorporated, in addition, Kanno discloses:
assigning, based on a size of each memory bank of the plurality of memory banks, the respective identifier to each block of the set of one or more memory blocks of the virtual memory(Kanno, [0226 -- The virtual block structure information table 33E shows data indicating the structure of each virtual block. The virtual block structure information table 33E includes an equivalent block size]);
and assigning, based on the respective identifier, each of the set of one or more memory blocks of the virtual memory to a respective memory bank of the plurality of memory banks(Kanno, [0137 -- Similarly, the virtual block allocate and erase command is one command obtained by combining a command function of instructing virtual block allocation and a command function of instructing virtual block erasure.]).
As per claim 9, the rejection of claim 1 is incorporated, in addition, Kanno discloses:
assigning one or more tags to each of one or more requests for one or more identifiers of one or more sets of one or more memory blocks of the virtual memory(Kanno, [0298 -- Further, queue IDs may be added to all commands and all command completion responses in order to identify which command has been executed. ]);
storing the one or more tags in a queue(Kanno, [0298 -- The host 2 may add the queue IDs to all commands]);
and removing a respective tag of the one or more tags from the queue responsive to outputting a respective identifier of the one or more identifiers associated with the respective tag(Kanno, [0299 -- Each command with priority “High” is queued in priority queue 61. Each command with priority “Medium” is queued in priority queue 62. Each command with priority “Low” is queued in priority queue 63. Extraction of a command from priority queue 61 takes preference of extraction of a command from priority queue 62 and extraction of a command from priority queue 63.]).
As per claim 11, the rejection of claim 1 is incorporated, in addition, Kanno discloses:
the set of one or more memory blocks of the virtual memory, which are subdivided into the plurality of memory banks, are of equal size(Kanno, [0206 -- FIG. 4 shows blocks for the physical NAND access management API 21 and blocks for the virtual NAND access management API 22. The blocks for the physical NAND access management API 21 and the blocks for the virtual NAND access management API 22 are managed by the SSD 3.]);
and storing the content in the set of one or more memory blocks of the virtual memory comprises:
and storing, responsive to a number of available memory blocks in the physical memory being at least a number of memory blocks in the set of one or more memory blocks of the virtual memory to be allocated to store the content, the content in the set of one or more memory blocks of the virtual memory(Kanno, [0335 -- (1) Block address, or block address and page address: This input parameter value(s) represents a physical address that designates a location in the NAND memory 5, to which data is to be written. ]).
As per claim 12, the rejection of claim 1 is incorporated, in addition, Kanno discloses:
comparing a number of available memory blocks in a reserved logical partition of memory blocks allocated responsive to receiving the content to be stored is less than the number of the set of one or more memory blocks of the virtual memory to be allocated to store the content(Kanno, [0320 -- The block-in-use list 71A indicates a list of blocks (physical blocks) that are included in the blocks of group #Y and hold valid data, i.e., a list of blocks currently used by the host 2. ]);
and selecting at least one of the available number of memory blocks in the physical memory as the storage location for the content wherein the identifier identifies the storage location for the content(Kanno, [0316 -- Block address: The virtual block address of an allocated virtual block is returned to the host 2.]).
Claim 13 is a system claim that is substantially similar to the method of claim 1, and therefore the same mappings will be incorporated.
Claim 16 is a system claim that is substantially similar to the method of claim 5 and therefore the corresponding mappings will be incorporated.
Claim 17 is a system claim that is substantially similar to the method of claim 9 and therefore the corresponding mappings will be incorporated.
Claim 19 is a system claim that is substantially similar to the method of claim 11 and therefore the corresponding mappings will be incorporated.
As per claim 20, Kanno discloses:
A non-transitory computer-readable medium comprising one or more computer-readable instructions that, when executed by at least one circuit(Kanno, [0104 -- The physical resources management processing and the command processing may be controlled by firmware executed by the CPU 12.]), cause the at least one circuit to perform a method comprising(Kanno, [0087 -- The controller 4 is electrically connected to the NAND memory 5 as a nonvolatile memory through a NAND interface 13, such as a toggle or ONFI. The controller 14 may have a physical resources management function for managing the physical resources of the SSD 3, namely, the NAND memory.]);
The remainder of claim 20 constitutes steps that are substantially similar to the method/steps of claim(s) 1 or 13 and therefore the same mappings will be incorporated.
As per claim 21, the rejection of claim 1 is incorporated, in addition, Kanno discloses:
wherein the second set of one or more memory blocks of the virtual memory are not associated with the identifier(Kanno, [0239 -- In this case, the combinations of the block addresses of a plurality of blocks belonging to a virtual block having, for example, virtual block address VB0, are determined as block address 0 of channel Ch.A, block address 0 of channel Ch.B, block address 0 of channel Ch.C, and block address 0 of channel Ch.D. Similarly, the combinations of the block addresses of a plurality of blocks belonging to a virtual block having, for example, virtual block address VB1, are determined as block address 1 of channel Ch.A, block address 1 of channel Ch.B, block address 1 of channel Ch.C, and block address 1 of channel Ch.D.]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanno(20170262175), and further in view of Post et al.(20130151830).
As per claim 6, the rejection of claim 5 is incorporated, in addition, Kanno does not explicitly disclose the following, however Post discloses:
wherein assigning the identifier comprises: generating a linked list of the set of one or more memory blocks of the virtual memory that store the content(Post, [0062 -- Tree 700 can include multiple nodes, where each node may be consistently sized for memory allocation purposes (e.g., each node may have a fixed size of 64 bytes). For the sake of simplicity, tree 700 is shown to include a small number of nodes.]);
and assigning the identifier to a first block of the linked list(Post, [0064 -- In some embodiments, each pointer field of an entry can have a value corresponding to a node pointer, an NVM pointer, an NVM-unmapped pointer, or an NVM-uncorrectable pointer. ]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Post into the system of Kanno for the benefit of realizing reconciling of the file system's view of data availabilities of LBAs with availability states of LBAs obtained from a data structure during system boot-up, and ensures that a NVM interface is able to communicate any inconsistencies to the file system at earlier time, thus enabling the file system to handle inconsistencies during system boot-up in a reliable manner(Post, 0074).
Claim(s) 10, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanno(20170262175), and further in view of Conklin et al.(20210073141).
As per claim 10, the rejection of claim 1 is incorporated, in addition, Kanno does not disclose the following, however Conklin discloses:
receiving, via one or more communication channels, one or more requests for one or more identifiers of one or more sets of one or more memory blocks of the virtual memory(Conklin, [0043 -- According to embodiments, when a read command is received from a host device by the controller 220 of the storage device 200, the hash value 606 may be retrieved from the forward mapping table entry 402 for the LBA specified by the read command]);
storing, for a respective request of the one or more requests, a respective channel identifier of each of the one or more communication channels associated with the respective request(Conklin, [0043 -- if a physical address value 602 specifying channel 2, die 5, block 2356, and page 9 is hashed by the hashing algorithm 604 described above to generate the hash value 606 shown in FIG. 6, then this value read from the forward mapping table 242 for the LBA of a read command]);
and transmitting the one or more requests via a plurality of second communication channels, wherein a first number of the one or more communication channels is less than a second number of the plurality of second communication channels(Conklin, [0044 -- In order to determine which of the physical locations read contains the target data corresponding to the requested LBA, the controller 220 may check metadata associated with the returned page data to determine which data to return to the host device]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Conklin into the system of Kanno for the benefit of storing in the forward mapping table is reduced by the size of the other two bits without increasing the read delay(Conklin, 0040).
Claim 18 is directed to implemented method/steps substantially similar to claim 10, and therefore the corresponding mappings are incorporated.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanno(20170262175), and further in view of Choi et al.(20240070067)).
As per claim 22, the rejection of claim 1 is incorporated, in addition, Kanno does not explicitly disclose the following, however Choi discloses:
clearing previously-stored content from the physical memory(Choi, [0226 -- After the reserved zone is opened, the memory controller 120 may trigger migration such that the data of the reserved zone are moved to the target zone. In an embodiment, the memory controller 120 may reset the reserved zone of the target zone when closing the target zone.], [0249 -- After the reserved zone is opened, the memory controller 120 may trigger migration such that the data of the reserved zone are moved to the target zone. In an embodiment, the memory controller 120 may reset the reserved zone of the target zone when closing the target zone.]), the clearing comprising applying, via each memory bank of a subset of the plurality of memory banks that store a second set of one or more memory blocks of the virtual memory, a reset signal to at least one block of the second set of one or more memory blocks of the virtual memory, wherein the subset of the plurality of memory banks does not store a block of the set of one or more memory blocks of the virtual memory and will not be in use during the storing of the content in the set of one or more memory blocks of virtual memory(Choi, [0226 -- In an embodiment, the memory controller 120 may reset the reserved zone of the target zone when closing the target zone. In an embodiment, the memory controller 120 may reset the reserved zone when the migration of the reserved zone is completed. In an embodiment, when the number of free erase units EU of the area dedicated to generate the reserved zone is smaller than a threshold value, the memory controller 120 may directly move the data of the reserved zone to the target zone and may reset the reserved zone. ], [0249 -- In an embodiment, the memory controller 120 may reset the reserved zone when the migration of the reserved zone is completed. In an embodiment, when the number of free erase units EU of the area dedicated to generate the reserved zone is smaller than a threshold value, the memory controller 120 may directly move the data of the reserved zone to the target zone and may reset the reserved zone.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Choi into the system of Kanno for the benefit of a memory device that is provided with multiple memory cells, where controller is configured to perform a write operation on a write unit included in the memory cells and an erase operation on an erase unit, thus improving the operating speed of the host device(Choi, 0634).
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanno(20170262175), and further in view of Goel et al.(2018/0081567).
As per claim 23, the rejection of claim 1 is incorporated, in addition, Kanno does not explicitly disclose the following, however discloses:
wherein the identifier is used to access the memory banks and to access the memory blocks instead of having to use the identifier to first look up a memory address of the memory banks on which the content is stored(Goel, [0033 -- With respect to the function call of “write”, a corresponding example command may be expressed as follows: write(bufH[12:0], page_offset[5:0], block_offset[1:0], data[64B], first, last); returns pass_fail. A write operation may provide the buffer handle, page_offset and block_offset within the memory buffer, as well as data corresponding to the block size quantum]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Goel into the system of Kanno for the benefit of A buffer allocator and memory management (BAM) mechanism that can be utilized to achieve on-demand, high-efficiency and high-performance buffer allocation and memory management. This allows external clients to use the same application programming interface (API) to interface with the BAM mechanism, independent of the physical organization and structure of the memory. The allocation of one or more blocks of memory is guaranteed when one is free and complete usage of existing memory enhances efficiency and renders fast allocation, high-throughput access and bounded access latency(Goel, [0011]).
Response to Arguments
Applicant's arguments filed 11/18/2025 have been fully considered but they are not persuasive.
Regarding the prior art rejections, the applicant argues that the prior art of record does not adequately teach the subject matter conveyed by the limitations of the amended claims. In particular, the applicant argues that the following limitation(s) from amended claims 1, 13 and 20 are not disclosed in the prior art of record:
…generating a buffer of storing the content in a set of one or more memory blocks of virtual memory, wherein the buffer of the set of one or more memory blocks of virtual memory is allocated for storing the content into one or more of a plurality of memory banks that subdivide the physical memory; assigning an identifier to the set of one or more memory blocks of the virtual memory that store the content to link the set of one or more memory blocks together in the buffer; and outputting the identifier for the set of one or more memory blocks of the virtual memory, the identifier to be used to access the set of one or more memory blocks where the content is stored…;(Remarks, p. 3, ’11’)
The USPTO disagrees. The generated buffer is an allocated space in storage/memory that stores data as clarified by the prior art of Kanno in the rejection of the respective claims. The identifier is also disclosed in Kanno as communicated to external agents, as clarified in the rejection of claims 1, 13 and 20. All rejections are maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132