Prosecution Insights
Last updated: October 02, 2026
Application No. 18/346,043

IMAGE SENSING DEVICE AND METHOD FOR MANUFACTURING THE SAME

Final Rejection §102§103
Filed
Jun 30, 2023
Priority
Jan 11, 2023 — RE 10-2023-0003903
Examiner
GRAY, AARON J
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
429 granted / 521 resolved
+14.3% vs TC avg
Strong +30% interview lift
Without
With
+29.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
32 currently pending
Career history
553
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
54.1%
+14.1% vs TC avg
§102
28.0%
-12.0% vs TC avg
§112
15.3%
-24.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 521 resolved cases

Office Action

§102 §103
Detailed Action Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 and 5-6 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Tojinbara et. Al. (US 20240113145 A1 hereinafter Tojinbara). Regarding claim 1, Tojinbara teaches in Figs. 25A-25B with associated text an image sensing device comprising: a pixel array including a plurality of unit pixels (23L and 23R) arranged therein (Fig. 25A, [0141]); and an isolation area 51 formed between the unit pixels, wherein the isolation area comprises a first isolation layer (portion of 521 under 25, examiner notes that 521 is disclosed as an impurity isolation region [0163] the claim would not necessarily require the isolation layer to be insulating) formed to have a first depth (see annotated Fig. below); a second isolation layer (portion of 521 under 25) formed to have a second depth (see annotated Fig. below); and a third isolation layer (portion of 521 between 25 and ) disposed between the first isolation layer and the second isolation layer and formed to have a third depth, the second depth is greater than the first depth (see annotated Fig. below). and wherein the third depth is greater than the first depth and the second depth (see annotated Fig. below, [0159], [0162]). PNG media_image1.png 373 374 media_image1.png Greyscale Regarding claim 5, Tojinbara teaches the third depth is a depth formed to provide full isolation (3rd depth extend completely through the substrate so that it provides full isolation where it is present). Regarding claim 6, Tojinbara teaches the control node region is formed in a corner region in a first diagonal direction of a unit pixel of the plurality of unit pixels (Fig. 25A). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et. Al. (US 20240030261 A1 hereinafter Hsu) and further in view of Tojinbara. Regarding claim 1, Hsu teaches in Figs. 1A-1C with associated text an image sensing device comprising: a pixel array including a plurality of unit pixels 103 arranged therein (Fig. 1A, [0018]); and an isolation area 112 formed between the unit pixels (Figs. 1A-1B, [0018]), wherein the isolation area comprises a first isolation layer 116m formed to have a first depth (Figs. 1A-1C, [0018]); a second isolation layer 116p formed to have a second depth (Figs. 1A-1C, [0018]); and a third isolation layer 114 disposed between the first isolation layer and the second isolation layer (114 is between 116p and 116m along the path through which the isolation area extends from 116p to 116m Fig. 1A) and formed to have a third depth, and wherein the third depth is greater than the first depth and the second depth 116 m and 116p do not extend all the way throughout the substrate however 114 does Figs. 1B and 1C also see [0055] and Fig. 16C). Hsu does not specify the second depth is greater than the first depth. Tojinbara teaches in Figs. 25A-25B wherein an isolation layer having a second depth greater than the first depth (see annotated Fig. below). and wherein a third depth is greater than the first depth and the second depth (see annotated Fig. below, [0159], [0162]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use an isolation structure with a depth profile similar to that of Tojinbara because according to Tojinbara by using such a structure and in particular by having such a first depth a second portion 522 can be accommodated (Fig. 25B) the second portion 522 functions as an overflow path (passage) through which signal charges pass when the signal charges move between the first photoelectric conversion portion 23L and the second photoelectric conversion portion 23R [0162]. Regarding claim 2, Hsu teaches the isolation area further includes a control node region 108 and a pixel transistor well region 110, and wherein the first isolation layer is formed on the control node region (Fig. 1B, [0019]-[0020]). Regarding claim 3, Hsu teaches the second isolation layer is formed on the pixel transistor well region (Fig. 1B). Regarding claim 5, Hsu teaches the third depth is a depth formed to provide full isolation (3rd depth extend completely through the substrate so that it provides full isolation where it is present). Regarding claim 6, Hsu teaches the control node region is formed in a corner region in a first diagonal direction (dotted diagonal line direction if Fig. 1A) of a unit pixel of the plurality of unit pixels (Fig. 25A). Regarding claim 7, Hsu teaches the pixel transistor well region (here the well region is that at the upper right) is formed in a corner region of the unit pixel in a second diagonal direction perpendicular to the first diagonal direction (Fig. 1A). Response to Arguments Applicant's arguments filed 07/01/2026 have been fully considered but they are not persuasive. Regarding the arguments on pages 6-7 Tojinbara teaches that 521 is disclosed as an impurity isolation region [0163] the claim would not necessarily require the isolation layer to be insulating as the claim never specifically recites that it is an insulating material isolation layers are well known in the art to be formed from doped material forming pn junction or insulating materials. Regarding the arguments on pages 7-8, the regions as identified above are distinguished from themselves and other structures by their depth and/or doping and are therefore interpreted to be firs second and third isolation layers. Regarding the arguments on pages 8-9 Hsu is not being relied upon to teach the new limitations of claim 1 instead Tojinbara is being relied upon see the 103 rejections above Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Toledo Fernando can be reached on 5712721867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AARON J GRAY/Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jun 30, 2023
Application Filed
Dec 15, 2023
Response after Non-Final Action
Apr 02, 2026
Non-Final Rejection mailed — §102, §103
Jul 01, 2026
Response Filed
Sep 01, 2026
Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12745466
Fin Field-Effect Transistor, ESD Protection Circuit, Filter Circuit, and Electronic Device
3y 6m to grant Granted Sep 22, 2026
Patent 12740331
JOSEPHSON JUNCTION DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 6m to grant Granted Sep 15, 2026
Patent 12733483
TRANSISTOR WITH SOURCE AND DRAIN VIA STRUCTURES
4y 1m to grant Granted Sep 08, 2026
Patent 12733274
IMAGING ELEMENT AND IMAGING DEVICE HAVING A POLYGONAL TRANSFER GATE OPENING
4y 0m to grant Granted Sep 08, 2026
Patent 12727484
INTERPOSER WITH CAPACITORS
4y 2m to grant Granted Sep 01, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
99%
With Interview (+29.8%)
2y 6m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 521 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month