Prosecution Insights
Last updated: August 17, 2026
Application No. 18/346,087

HIGH CONDUCTIVITY TRANSISTOR CONTACTS COMPRISING GALLIUM ENRICHED LAYER

Non-Final OA §102
Filed
Jun 30, 2023
Examiner
ERDEM, FAZLI
Art Unit
Tech Center
Assignee
Intel Corporation
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
919 granted / 1077 resolved
+25.3% vs TC avg
Strong +16% interview lift
Without
With
+16.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
27 currently pending
Career history
1100
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
50.2%
+10.2% vs TC avg
§102
37.9%
-2.1% vs TC avg
§112
7.5%
-32.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1077 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gluschenkov et al. (20170213889). Regarding Claim 1, in Figs. 1, 8a and 8b and in paragraphs 0026-0049, Gluschenkov et al. discloses an apparatus, comprising: a substrate 102 comprising silicon (paragraph 0027); a first layer of a source or drain region of a p-type transistor, the first layer 106 positioned above the substrate, the first layer comprising boron, silicon and germanium (paragraph 0045); a second layer 802 coupled to the source or drain region, the second layer comprising a metal contact for the source or drain region (see paragraphs 0047 and 0048); and a third layer 402/602 positioned between the first layer and the second layer, the third layer comprising at least one monolayer comprising gallium (see paragraphs 0043 and 0044), wherein the third layer is adjacent to the first layer. Regarding Claim 2, the first layer 106 comprises epitaxially grown boron doped silicon germanium, and the third layer comprises epitaxially grown boron doped silicon germanium with a higher concentration of germanium than the first layer (see paragraph 0035). Regarding Claim 3, the third layer 402/602 is between 10-20 nanometers thick (see paragraph 0034) Regarding Claim 4, a fourth layer 702 between the second layer and the third layer, the fourth layer comprising at least one of titanium, nickel, or platinum (see paragraph 0047). Regarding Claim 5, the second layer 802 comprises at least one of cobalt or tungsten (see paragraph 0048). Regarding Claim 6, a concentration of gallium in a top two monolayers of the third layer is within a range of 5E19 to 5E20 atoms/cm3 (see paragraphs 0039 and 0040) Regarding Claim 7, the first layer 106 comprises both B-11 and B-10 isotopes of boron (see paragraph 0030). Regarding Claim 8, the apparatus is an integrated circuit component (see transistor which is an integrated circuit component in paragraph 0030). Regarding Claim 9, the apparatus further comprises: a printed circuit board; and a first integrated circuit component attached to the printed circuit board, the first integrated circuit component comprising the substrate, the first layer, the second layer, and the third layer. Regarding Claim 10, in paragraphs 0032 and 0038, the apparatus further comprises one or more second integrated circuit components attached to the printed circuit board. Regarding Claim 11, in Figs. 1, 8a and 8b and paragraphs 0026-0049, Glushenkov et al. discloses.an apparatus, comprising: a substrate 102 comprising silicon (paragraph 0027); a first layer 106 positioned adjacent to the substrate (paragraph 0045), the first layer comprising boron, silicon and germanium (see paragraph 0045); a second layer 402/602 positioned adjacent to the first layer, the second layer comprising gallium (see paragraph 0043 and 0044); and a third layer 802 positioned adjacent to the second layer, the third layer comprising a metal (see paragraph 0048). Regarding Claim 12, a concentration of gallium in the second layer is within a range of 5E19 to 5E20 atoms/cm3. (see paragraphs 0039 and 0040) Regarding Claim 13, the first layer comprises epitaxially grown boron doped silicon germanium and the second layer comprises epitaxially grown boron doped silicon germanium with a higher concentration of germanium than the first layer (see paragraph 0035) Regarding Claim 14, an atomic percentage of gallium in a portion of the second layer below a top two monolayers of the second layer is less than five percent (see paragraph 0050) Regarding Claim 15, the third layer comprises at least one of titanium, nickel, platinum, cobalt, or tungsten (see paragraph 0047). Regarding Claim 16, in Figs, 1-8b and paragraphs 0026-0049, Gluschenkov et al. discloses. a method, comprising: forming a first layer 106 comprising boron, silicon, and germanium (paragraph 0045), the first layer positioned above a substrate; forming a second layer 402/602 positioned adjacent to the first layer, the second layer comprising gallium (see paragraphs 0043 and 0044); and forming a third layer 802 comprising metal, the third layer located on the second layer (see Fig. 8a/8b, elements 802 and 402/602). Regarding Claim 17, in paragraph 0037, forming the second layer comprises applying triethyl gallium on the first layer. Regarding Claim 18, in paragraph 0037, forming the second layer comprises applying trimethyl gallium to the first layer. Regarding Claim 19, in paragraph 0035, forming the second layer comprises applying a precursor comprising gallium to the first layer at a temperature of between 375 and 500 degrees Celsius. Regarding Claim 20, a concentration of gallium in a portion of the second layer is within a range of 5E19 to 5E20 atoms/cm3. (see paragraph (see paragraphs 0039 and 0040). Examiner is including following pertinent prior art references that are NOT relied upon but that do disclose the usage of gallium layer to lower contact resistance. Peng et al. 20190165174 Holland et al. 20210066499 Glass et al. 20150054031 Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAZLI ERDEM/Primary Examiner, Art Unit 2812 7/22/2026
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Prosecution Timeline

Jun 30, 2023
Application Filed
Nov 15, 2023
Response after Non-Final Action
Jul 24, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+16.0%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1077 resolved cases by this examiner. Grant probability derived from career allowance rate.

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