Attorney Docket Number: 138785-5218-US
Filing Date: 7/03/2023
Claimed Foreign Priority Date: 11/17/2022 (KR10-2022-0154699)
Inventors: Cha et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendments/arguments filed on 12/12/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Acknowledgement
The Amendment filed on 12/12/2025, responding to the Office action mailed 9/24/2025, has been entered. Applicant amended claims 1, 5, and 12, and added claim 21. The present Office action is made with all the suggested amendments being fully considered.
Response to Arguments/Amendments
Applicant’s amendments to the claims have overcome the claim objections and claim rejections under 35 U.S.C. 102 and 35 U.S.C. 103 as previously formulated in the Non-Final Office action mailed on 9/24/2025. In addition, the arguments to the rejection of claim 14 is found persuasive. In addition, the drawing objection has been withdrawn, per the additional drawing sheet. Accordingly, the claim objections and claim rejections of 35 U.S.C. 102 and 35 U.S.C. 103 are hereby withdrawn. Accordingly, pending in this application are claims 1-21. New grounds of rejections are presented below, however, as necessitated by applicant’s amendments to the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20170025384 A1) in view of Vaidya (US 20190006264 A1) further in view of Moon (US 20240071986 A1).
Regarding claim 1, Park (see, e.g., fig. 6) shows most aspects of the instant invention including a semiconductor chip (e.g., semiconductor package 200) comprising:
A semiconductor substrate (e.g., semiconductor substrate 120 + FEOL structure 130) that includes an upper surface (e.g., top surface of substrate 120) and a lower surface (e.g., bottom surface of FEOL structure 130) opposite to the upper surface (e.g., top surface of substrate 120), and a center pad (e.g., left-side connection pad 80) disposed on a central portion (see, e.g., annotated fig. 1 below) of the upper surface and an edge pad (e.g., right-side connection pad 80) disposed on the upper surface (e.g., top surface of substrate 120);
a wiring structure (e.g., multi-layered wiring structure 146 + inter-metal insulating layer 148) that includes a wiring insulating layer (e.g., inter-metal insulating layer 148) disposed on the lower surface (e.g., bottom surface of FEOL structure 130) of the semiconductor substrate (e.g., semiconductor substrate 120 + FEOL structure 130) and a wiring pattern (e.g., metal wiring layers 142 of multi-layered wiring structure 146) disposed in the wiring insulating layer (e.g., inter-metal insulating layer 148) and electrically connected to the semiconductor substrate (e.g., semiconductor substrate 120 + FEOL structure 130);
a first bump pad (e.g., left-side bonding pad 152) disposed on a first surface (see, e.g., fig. 5 (cross section of fig. 6)) of the wiring structure (e.g., multi-layered wiring structure 146 + inter-metal insulating layer 148) and electrically connected to the wiring pattern (e.g., metal wiring layers 142 of multi-layered wiring structure 146);
a first connection bump (e.g., left-side connection terminal 154 + paragraph 106 “The connection terminal 154...may each include... a solder bump...”) that connects the first bump pad (e.g., left-side bonding pad 152) to an external device (see, e.g., connection to second device in annotated Fig. 1 below);
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Annotated Fig. 1
Park (see, e.g., fig. 6), however, fails to show the edge pad having a different shape and a larger surface area compared to the center pad, and that the edge pad is disposed on an edge portion of the device.
Vaidya (see, e.g., figs. 9A and 9B), in a similar device to Park, teaches an edge pad (e.g., bond pad 911) having a larger surface area (see, e.g., fig. 9B) compared to a center pad (e.g., bond pad 907), and that the edge pad (e.g., bond pad 911) is disposed on an edge portion of the device.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the edge portion configuration and large surface area of Vaidya within the device of Park, in order to achieve the expected result of providing additional surface area for additional conductive bumps in later steps of the manufacturing process and include additional conductive pads for edge regions of the substrate as desired.
Park in view of Vaidya, however, fails to teach that the edge pad has a different shape compared to the center pad.
Moon (see, e.g., fig. 3), in a similar device to Park in view of Vaidya, teaches conductive pads that can possess any polygon shape (see, e.g., paragraph 35 “…conductive pads 225 may have footprints (layout) resembling circles, ellipses, race-tracks, rectangles with dissimilar widths and lengths, or any polygon shapes”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the variety of the contact pad shapes of Moon within the central and edge pads of Park in view of Vaidya, decreasing resistance within the device due to the expanded contact area and diversifying the contact pad geometry to meet various conductivity requirements as desired.
Regarding claim 5, Park (see, e.g., fig. 6) shows a second bump pad (e.g., right-side bonding pad 152) disposed on the first surface (see, e.g., fig. 5 (cross section of fig. 6)) of the wiring structure (e.g., multi-layered wiring structure 146 + inter-metal insulating layer 148) and electrically connected to the wiring pattern (e.g., metal wiring layers 142 of multi-layered wiring structure 146), and a second connection bump (e.g., right-side connection terminal 154 + paragraph 106 “The connection terminal 154...may each include... a solder bump...”) that connects the second bump pad (e.g., right-side bonding pad 152) to an external device (see, e.g., connection to second device in annotated Fig. 1 above).
Regarding claim 9, Park (see, e.g., fig. 6) shows the second bump pad (e.g., right-side bonding pad 152) is spaced apart from the first bump pad (e.g., left-side bonding pad 152).
Regarding claim 11, Park (see, e.g., fig. 6) shows the first connection bump (e.g., left-side connection terminal 154 + paragraph 106 “The connection terminal 154...may each include... a solder bump...”) and the second connection bump (e.g., right-side connection terminal 154 + paragraph 106 “The connection terminal 154...may each include...a solder bump...”) include solder (see, e.g., paragraph 106 “The connection terminal 154…may each include… a solder bump…”).
Claims 2 and 6 rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Vaidya further in view of Moon and Liu (US 20220344291 A1).
Regarding claim 2, Park in view of Vaidya further in view of Moon fails to teach a thickness of the center pad in a vertical direction ranges from 2 µm to 3 µm.
Liu (see, e.g., fig. fig. 12), in a similar device to Park in view of Vaidya further in view of Moon, teaches the thickness of a bond pad (e.g., bond pad structure 130) in a vertical direction ranges from 2 µm to 3 µm (see, e.g., paragraph 54 “In some embodiments, the bond pad structure 130”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the bond pad thickness of Liu in the center pad of Park in view of Vaidya further in view of Moon, in order to achieve the expected result of limiting the pad to a short vertical length, minimizing the cost of fabricating the conductive portion.
Regarding claim 6, Liu (see, e.g., fig. fig. 12), in a similar device to Park in view of Vaidya further in view of Moon, teaches the thickness of a bond pad (e.g., bond pad structure 130) in a vertical direction ranges from 2 µm to 3 µm (see, e.g., paragraph 54 “In some embodiments, the bond pad structure 130”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the bond pad thickness of Liu in the edge pad of Park in view of Vaidya further in view of Moon to the same thickness as the center pad, in order to achieve the expected result of limiting the pad to a short vertical length, minimizing the cost of fabricating the conductive portion.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Vaidya further in view of Moon and Kim (US 5804883 A).
Regarding claim 3, Park in view of Vaidya further in view of Moon fails to teach the center pad has a regular octagon shape with a side length of 1 µm.
Kim (see, e.g., fig. 2), in a similar device to Park in view of Vaidya further in view of Moon, teaches a pad has a regular octagon shape (e.g., regular octagon 20).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to adopt the octagon shape of Kim within the center pad of Park in view of Vaidya further in view of Moon, in order to decrease the concentration of stress (for example, onto a square’s four corners) onto corners of the bonding pad due to the thermal expansion coefficients (see paragraph 6 of Kim).
In addition, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to limit each side of the octagon-conductive pad to a length of 1 µm, since it has held that where the general condition of a claim is disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art.
Claims 4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view Vaidya further in view of Moon and Chang (US 20230140683 A1).
Regarding claim 4, Park in view of Vaidya further in view of Moon fails to teach a material of the center pad includes nickel.
Chang (see, e.g., fig. 5A), in a similar device to Park in view of Vaidya further in view of Moon, teaches a material of a conductive pad (e.g., bond pad 516) includes nickel (see, e.g., paragraph 76 “Bond pads 516 may be formed of copper, aluminum, nickel…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the nickel of Chang in the center pad of Park in view of Vaidya further in view of Moon, as nickel was a well-known medium at the time of filing the invention to be an included material within a conductive pad, as taught by Chang.
Regarding claim 8, Chang (see, e.g., fig. 5A), in a similar device to Park in view of Vaidya further in view of Moon, teaches a material of a conductive pad (e.g., bond pad 516) includes nickel (see, e.g., paragraph 76 “Bond pads 516 may be formed of copper, aluminum, nickel…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the nickel of Chang in the center pad of Park in view of Vaidya further in view of Moon, as nickel was a well-known medium at the time of filing the invention to be an included material within a conductive pad, as taught by Chang.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view Vaidya further in view of Moon, Kim, and Aoki (US 20230317652 A1).
Regarding claim 7, Park in view of Vaidya further in view of Moon fails to teach the edge pad has an extended octagon shape formed by extending squares, each having a side length of 1 µm, from four non-continuous sides of a regular octagon that has a side length of 1 µm.
Kim (see, e.g., fig. 2), in a similar device to Park in view of Vaidya further in view of Moon, teaches a pad has a regular octagon shape (e.g., regular octagon 20).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to adopt the octagon shape of Kim within the center pad of Park in view of Vaidya further in view of Moon, in order to decrease the concentration of stress (for example, onto a square’s four corners) onto corners of the bonding pad due to the thermal expansion coefficients (see paragraph 6 of Kim).
In addition, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to limit each side of the octagon-conductive pad to a length of 1 µm, since it has held that where the general condition of a claim is disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art.
Park in view of Vaidya further in view of Moon and Kim, however, fails to teach an extended octagon shape formed by extending squares, each having a side length of 1 µm, from four non-continuous sides of the rectangular octagon.
Aoki (see, e.g., fig. 3), in a similar device to Park in view of Vaidya further in view of Moon and Kim, teaches extending squares formed onto a circular pad (see, e.g., pad 226K).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the extending square pads of Aoki onto the octagon corners of Park in view of Vaidya further in view of Moon and Kim, in order to provide escape directions for heated, flowing solder from the solder bump (note that connection pad 80 may include solder material, see paragraph 60 of Park).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Park (hereinafter Park1) in view of Vaidya further in view of Moon and Park (US 20220392866 A1) (hereinafter Park2).
Regarding claim 10, Park1 in view of Vaidya further in view of Moon fails to teach a material of the first bump pad and a material of the second bump pad include at least one of copper or nickel.
Park2 (see, e.g., fig. 1D), in a similar device to Park1 in view of Vaidya further in view of Moon, teaches a material of a first bump pad (e.g., left-side bump pad 95) and a material of the second bump pad (e.g., right-side bump pad 95) include at least one of copper or nickel (see, e.g., paragraph 34 “The bump pad 95 may include a metal such as copper (Cu)…nickel(Ni)…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the copper or nickel of Park2 within the bump pads of Park1 in view of Vaidya further in view of Moon, as copper and nickel were well-known mediums at the time of filing the invention to be an included material within a bump pad, as taught by Park2.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Park1 in view of Vaidya further in view of Moon and Kim (US 20190221520 A1) (hereinafter Kim2).
Park1 in view of Vaidya further in view of Moon fails to teach defining an end of one side surface of the semiconductor substrate as a point S1, an end of another side surface of the semiconductor substrate as a point S4, dividing a distance between the point S1 and the point S4, defining a point close to the point S1 as a point S2, a point distant from the point S1 as a point S3, and a central point between the one side surface and the another side surface as a point C, the center pad is disposed in an area between the points S2 and S3, and the edge pad is disposed in an area between the points S1 and S2 and a second edge pad is disposed in an area between the points S2 and S3.
Kim2 (see, e.g., fig. 2A), in a similar device to Park1, teaches a center pad (e.g., central pad 25) disposed in an area between the area between the points S2 and S3, and the edge pad (e.g., left edge pad 25) is disposed in an area between the points S1 and S2 and a second edge pad (e.g., left edge pad 25) is disposed in an area between the points S2 and S3, and a central point between the one side surface and the another side surface as a point C (see, e.g., annotated figure 2 below).
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Annotated Fig. 2
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the pad-placement geometry of Kim2 onto the substrate of Park 1, in order to achieve the expected result of providing additional conductivity throughout different portions of the substrate’s surface, as opposed to restricting it to one given area. Note that the edge pad of Park1 would need to be duplicated in order to provide one on the other side of the substrate, opposite the edge pad’s placement. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to duplicate the edge pad of Park1 to form additional conductivity regions within the substrate, since it has been held that a mere duplication of working parts of a device involves only routine skill in the art. In re Harza 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04.
Regarding claim 13, Park1 in view of Kim2 teaches when a thickness of the semiconductor substrate is reduced, the point S2 shifts to a point S22 between the points S2 and C, the point S3 shifts to a point S33 between the points S3 and C, and the points S22 and S33 are spaced apart from the point C by a same distance (see, e.g., annotated figure 3 below).
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In reference to the claim language referring to the shifting of points on a substrate when a thickness of the semiconductor substrate is reduced, intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963); Ex parte Masham, 2USPQ2d 1647 (Bd. Pat/ App. & Inter. 1987). In the instant case and as explained above, Park1 in view of Kim2 shows all structural limitations specifically recited in the claim and shifting the areas of points involves a mere manipulation of the thickness within the substrate; it appears that the recited functional limitation does not affect the structure of Park1 in view of Kim2’s bonding structure.
Claims 14-15, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Albers (US 20150333022 A1) in view of Moon further in view of Lee (US 20200135636 A1).
Regarding claim 14, Albers (see, e.g., 5) shows most aspects of the instant invention, including a semiconductor package (e.g., IC package 102) comprising:
A first base (e.g., circuit board 104) that includes a semiconductor substrate (e.g., substrate inherent to circuit board 104);
A center pad (e.g., central conventional contact pad 110”) disposed at a central portion (e.g., center of the substrate) of an upper surface (e.g., top surface of circuit board 104) of the semiconductor substrate (e.g., substrate inherent to circuit board 104);
An edge pad (e.g., edge conventional contact pad 110) disposed on the outer portion (e.g., edge of substrate) of the upper surface of the base (e.g., substrate inherent to circuit board 104);
A second semiconductor chip (e.g., substrate 106 + die 108 of IC package 102) stacked on the first base (e.g., circuit board 104);
A first connection bump (e.g., solder bridge 124b + 124c + paragraph 34 “In Fig. 5, the solder joints 124b + 124c have come in contact, forming a solder bridge”) disposed between the first base (e.g., circuit board 104) and the second semiconductor chip (e.g., substrate 106 + die 108 of IC package 102) and that contacts the center pad (e.g., central conventional contact pad 118); and
A second connection bump (e.g., solder joint 124a on edge of circuit board 104);
disposed between the first base (e.g., circuit board 104) and the second semiconductor chip (e.g., substrate 106 + die 108 of IC package 102) and that contacts the edge pad (e.g., edge conventional contact pad 110);
Albers (see, e.g., fig. 5), however, fails to explicitly show the edge pad differs from a shape of the center pad.
Moon (see, e.g., fig. 3), in a similar device to Albers, teaches conductive pads that can possess any polygon shape (see, e.g., paragraph 35 “…conductive pads 225 may have footprints (layout) resembling circles, ellipses, race-tracks, rectangles with dissimilar widths and lengths, or any polygon shapes”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the conductive pad polygon shape of Moon within the center pad of Albers, making contact with the entire solder bridge between the semiconductor chips, decreasing resistance within the device due to the expanded contact area. Note that the edge pads of Albers (e.g., conventional contact pad 110) have a circular footprint (see, e.g., paragraph 28).
Albers in view of Moon, however, fails to explicitly teach the first base is a semiconductor chip.
Lee (see, e.g., fig. 8), in a similar device to Albers in view of Moon, teaches a base (e.g., base 10) is a semiconductor chip (see, e.g., paragraph 59 “…the base 10 may be a printed circuit board or a semiconductor chip”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include semiconductor chip configuration of Lee within the structure of Albers in view of Moon, in order to achieve the expected result of providing any electronic components within the base as desired. In addition, note that Lee explicitly shows the base can be a circuit board or a chip, noting that Albers discloses the base as a circuit board, so the two components are used in substantially similar areas and configurations.
Regarding claim 15, Moon (see, e.g., fig. 3) teaches the center pad has a polygonal shape (see rejection directly above).
Albers in view of Moon does not explicitly teach the edge pad includes a center pad portion and a protruding pad portion that extends from an edge of the center pad portion in a lateral direction.
In an alternate embodiment of Albers (see, e.g., fig. 16), however, the contact pad includes a polygonal center pad portion (e.g., metal recess portion 154) and a protruding pad portion (e.g., metal projection pad 152) that extends from an edge of the center pad portion (e.g., metal recess portion 154) in a lateral direction (e.g., note that the projection portion 152 extends directly from the edge of the recess portion).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to combine the alternate embodiment and the primary embodiment of Albers, in order to achieve the expected result of providing a central contact recess portion to surround the solder bump as necessary. In addition, note that Albers discloses any of the contact pads of the IC package can adopt any of the alternate embodiment pads revealed within figures 15 to 18 (see paragraph 50 of Albers).
Regarding claim 18, Albers (see, e.g., fig. 5) shows the second connection bump (e.g., solder joint 124a on edge of circuit board 104) continuously contacts side surfaces (e.g., contact surface between connection bump and edge pad) of the protruding portions (see, e.g., alternative embodiment of Albers above) of the edge pad (e.g., edge conventional contact pad 110).
In addition, see the rationale stated in the paragraphs above with respect to claims 14-15 regarding the alternate embodiment of Albers, which are considered to be repeated here.
Regarding claim 20, Albers in view of Moon further in view of Lee teaches the second semiconductor chip (e.g., substrate 106 + die 108 of IC package 102) overlaps the first semiconductor chip (e.g., first base/printed circuit board 104 modified to a semiconductor chip) in a vertical direction.
Albers in view of Moon, however, fails to explicitly teach this overlapping is done without a warpage phenomenon.
In an alternate embodiment of Albers (see, e.g., fig. 4), however, the second semiconductor chip overlaps the first base in a vertical direction without a warpage phenomenon.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to modify the chips of Albers in view of Moon to the non-warped geometry in the alternate embodiment of Albers, in order to achieve the expected result of preventing potential manufacturing defects and long-term performance as a result of the chip’s warping.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Albers in view of Moon further in view of Lee and Aoki.
Regarding claim 16, Albers in view of Moon fails to teach each of the protruding pad portions of the edge pad has a square shape.
Aoki (see, e.g., fig. 3), in a similar device to Albers in view of Moon further in view of Lee, teaches protruding pad portions have square shapes (see, e.g., pad 226K).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the extending square pads of Aoki onto the protrusion portions of Albers in view of Moon, in order to provide escape directions for heated, flowing solder from the solder contacts (note that the conductive joints are solder, see paragraph 29 of Albers).
Regarding claim 17, Albers in view of Moon further in view of Lee fails to teach the protruding pad portions of the edge pad are spaced apart from each other along an edge of the center pad portion (note that the protruding pads).
Aoki (see, e.g., fig. 3), in a similar device to Albers in view of Moon further in view of Lee, teaches the protruding pad portions are spaced apart from each other along an edge of a center pad portion.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the protruding pad portions of Aoki among the corners of the pads of Albers in view of Moon further in view of Lee, in order to provide escape directions for heated, flowing solder from the solder contacts (note that the conductive joints are solder, see paragraph 29 of Albers) within different regions along the edge of the center pad portion.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Albers in view of Moon further in view of Lee and Ohba (US 20220208710 A1).
Regarding claim 19, Albers in view of Moon further in view of Lee fails to teach a thickness between an upper surface and a lower surface of each of the first semiconductor chip and the second semiconductor chip is equal to or less than 37 µm.
Ohba (see, e.g., fig. 1), in a similar device to Albers in view of Moon further in view of Lee, teaches the thickness between a first semiconductor chip (e.g., semiconductor chip stack 30) and a second semiconductor chip (e.g., semiconductor chip 40) is equal to or less than 37 µm (see, e.g., paragraph 30 “The distance between facing lateral faces of the semiconductor chip stack 30 and the semiconductor chip 40 can be made, for example, about 10 μm to about 100 μm”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to use the distance within Ohba as the distance between chips of Albers in view of Moon further in view of Lee, in order to achieve the expected result of maintaining a small scale of conductive contacts between the chips, preserving room and space for other potential additions to the device while minimizing the cost of manufacturing while fabricating the device.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Vaidya further in view of Moon and Chen (US 20220068860 A1).
Regarding claim 21, Park in view of Vaidya further in view of Moon fails to teach wherein the wiring structure and the center pad are electrically separated by the semiconductor substrate.
Chen (see, e.g., fig. 28), in a similar device to Park in view of Vaidya further in view of Moon, teaches a wiring structure (e.g., wire bonds 712) and contact pads (e.g., bond pads 706) are electrically separated (see, e.g., paragraph 70 “…the substrate 702 may be a silicon-on-insulator (SOI) substrate.”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the SOI substrate configuration of Chen within the setup of Park in view of Vaidya further in view of Moon (including omitting the TSV structure of Park (fig. 6) in view of Vaidya further in view of Moon, such as in Chen), in order to achieve the expected result of isolating opposing sides of the substrate, dividing regions of electronic components as necessary and increasing signal processing speed within the device.
Conclusion
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814