Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed February 20, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 4, 7, 13, 16
b. Pending: 1, 4-7, 11, 13-20
Claims 1, 7, and 16 have been amended and claims 2-3, 8-10, and 12 have been previously canceled.
Response to Arguments
Applicant’s arguments with respect to claims 1, 4-7, 11, and 13-20 have been considered but are moot because the new ground of rejection relies on newly found references along with previously used references applied in the prior rejection of record. New grounds of rejection are made in view of Dong et al. (US Pub. 20110273935 A1; “Dong”, Ju (US Pub. 20060114723 A1), and Mokhlesi et al. (US Pub. 20040156241 A1; “Mokhlesi”). Dong para. [0084] and Fig. 13 are relevant to claims 1, 7, and 16. Ju para. [0025] and Fig. 1 are relevant to claim 4, and Mokhlesi para. [0014] is relevant to claim 16.
Claim Objections
The objections to claims 7 and 16 are withdrawn pursuant to claim amendments.
Claim 4 is objected to because of the following informality: on p.3, lines 2-3, add an “a” before “second precharge circuit”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The rejections of claims 1, 7, and 11 under 35 U.S.C. 112(a) have been withdrawn pursuant to claim amendments.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pub. 20090010068 A1) in view of Dong (US Pub. 20110273935 A1) and Guterman (US Pub. 20070091685 A1).
Regarding independent claim 1, Lee discloses a memory device (Fig. 8: flash memory system; [0050]) comprising:
a bit line (bit lines BLs; [0050]) coupled to a memory cell (memory cell array 302 contains memory cells; [0050]);
a page buffer (Fig. 20: first data latch 602; [0107]) configured to generate a latch signal based on program data and a voltage level of a sensing node ([0107]: In addition to storing read data and program data, the data latches can store the results of sensing in order to provide an enable voltage, inhibit voltage, or intermediate voltage to a bit line in accordance with the sensed state of the storage element relative to its target state, including coarse verify levels and final verify levels), which is coupled to the bit line (a sensing node may be coupled to a bit line BL, see annotated image below; [0107]: The sense amplifier is selectively connected to the selected bit line by selecting one of signals of "evenBL" and "oddBL."),
Lee does not disclose:
a precharge control circuit configured to disable a bit line precharge signal during a coarse program operation and to enable the bit line precharge signal during a fine program operation; and
a voltage level of a sensing node, which is coupled to the bit line, configured to precharge the bit line according to the latch signal to perform a coarse verification when the bit line precharge signal is disabled, and configured to precharge the bit line regardless of the latch signal to perform a fine verification when the bit line precharge signal is enabled.
However, Dong teaches:
a coarse program operation ([0084]: In some embodiments, programming has a coarse mode and a fine mode. In general, a coarse programming mode may attempt to program a memory cell faster when it is further from its target threshold voltage, and program more slowly when the memory cell is closer to its target threshold voltage) and a fine program operation ([0084]); and
a voltage level of a sensing node, which is coupled to the bit line, configured to precharge the bit line according to the latch signal to perform a coarse verification when the bit line precharge signal is disabled (in reference to Fig. 13, per [0141]: In step 1302, a coarse verify of the A-state is performed…Step 1302 may include sensing bit lines for conduction current and storing a value in a QPW latch based on whether the bit line conducts a significant current), and configured to precharge the bit line regardless of the latch signal to perform a fine verification when the bit line precharge signal is enabled ([0087]: If, in step 754, it is determined that the memory cell was in the fine programming mode, then a fine verification conditions are applied and sensing will be performed in step 770…In some embodiments, even after the memory cell is inhibited from further programming, its bit line may be charged during verify of step 770; [0060]: a predetermined state latched in bit line latch 482 will result in the connected bit line being pulled to a state designating program inhibit (e.g., Vdd). Examiner concludes that program inhibition is associated with the latch signal, so per [0087] and [0060], Dong teaches that bit line charging occurs during fine verification regardless of the latch signal).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Dong to Lee wherein there is a coarse program operation, a fine program operation, and a voltage level of a sensing node, which is coupled to the bit line, configured to precharge the bit line according to the latch signal to perform a coarse verification when the bit line precharge signal is disabled, and configured to precharge the bit line regardless of the latch signal to perform a fine verification when the bit line precharge signal is enabled in order to reduce or eliminate differences in channel coupling between program verify and read (Dong, [0041]).
Also, through Guterman:
a precharge control circuit configured to disable a bit line precharge signal during a coarse program operation ([0114]: When C/F register 420 indicates that the floating gate 56' is in the coarse mode, the switch 700 will select input 702 which will be the normal components connected to the bit line during the coarse programming mode. That is, during coarse programming mode, in one embodiment, there is no charge packet metering) and to enable the bit line precharge signal during a fine program operation ([0114]: If floating gate 56' is in the fine programming mode, as indicated by C/F register 420, switch 700 will connect terminal 51 ' to switch 708 and capacitor 710. The opposite side of capacitor 710 is connected to a reference potential (e.g. ground). Switch 708 is connected to a pre-charge supply (e.g., voltage supply) 712); and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Guterman to modified Lee wherein the memory device comprises a precharge control circuit configured to disable a bit line precharge signal during a coarse program operation and to enable the bit line precharge signal during a fine program operation in order to provide tighter threshold voltage distributions and shorter programming times for coarse and fine programming (Guterman, [0016]).
Independent claim 7 contains limitations that are substantially the same in claimed subject matter to the limitations of claim 1 and therefore claim 7 is rejected for the same reasons as independent claim 1.
Regarding claim 11, Lee, Dong, and Guterman together disclose the limitations of claim 7. Further, through Lee:
wherein the verification information signal is at least one of: a logic value of a memory cell distribution; a verification voltage (per [0017], the threshold voltage of the memory cell is lower than the final target level V.sub.vA2); and a number of times that a program operation is performed.
Claims 4-6 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pub. 20090010068 A1) in view of Ju (US Pub. 20060114723 A1).
Regarding independent claim 4, Lee discloses a memory device (Fig. 8: flash memory system) comprising:
a bit line (BLs) coupled to a memory cell ([0050]);
a precharge control circuit (316) configured to generate a bit line precharge signal based on a program operation information signal ([0082]: The selected bit line BL.sub.n is set up or biased according to the data to be programmed into the memory cell of the selected word line at that particular bit line. Examiner asserts that the “data to be programmed into the memory cell” is analogous to a program operation information signal); and
Lee does not disclose:
a page buffer configured to generate a latch signal based on program data and a voltage level of a sensing node, which is coupled to the bit line, and configured to precharge the bit line responsive to at least one of the bit line precharge signal and the latch signal,
wherein the page buffer comprises a first precharge circuit configured to apply a core voltage to the bit line responsive to the bit line precharge signal; second precharge circuit configured to apply the core voltage to the bit line responsive to the latch signal;
and a sensing latch circuit configured to generate the latch signal responsive to the voltage level of the sensing node,
wherein the first precharge circuit and the second precharge circuit are coupled in parallel to the bit line.
However, Ju teaches:
a page buffer (Fig. 1; [0019]: FIG. 1 is a circuit diagram of a page buffer) configured to generate a latch signal (voltage level of a node QB; [0024]) based on program data ([0025]: data received from the I/O pad YA; [0026]: A NMOS transistor N115 is driven according to a program signal PGM so that data to be programmed, which are stored in the main latch 110, are transmitted to a selected bit line in a program operation) and a voltage level of a sensing node (node SO; [0027]: a voltage level of the node SO varies depending upon the status of a cell, and a voltage of the input terminal QBb and the output terminal QB of the main latch 110 varies accordingly), which is coupled to the bit line (even bit line BLe or odd bit line BLo), and configured to precharge the bit line responsive to at least one of the bit line precharge signal and the latch signal ([0010]: The page buffer further includes a first switch for precharging the even bit line or the odd bit line by supplying a predetermined voltage to the sensing node according to a precharge signal and a main register for storing state data of the selected cell according to a voltage level of the sensing node and a main latch signa),
wherein the page buffer (Fig. 1) comprises a first precharge circuit (PMOS transistor P102; [0024]) configured to apply a core voltage (power supply voltage Vcc; [0024]) to the bit line responsive to the bit line precharge signal (precharge signal PRECHb); second precharge circuit (PMOS transistor P103) configured to apply the core voltage to the bit line responsive to the latch signal (QB; [0024]);
and a sensing latch circuit (main latch 110; [0024]) configured to generate the latch signal responsive to the voltage level of the sensing node ([0027]: a voltage level of the node SO varies depending upon the status of a cell, and a voltage of the input terminal QBb and the output terminal QB of the main latch 110 varies accordingly),
wherein the first precharge circuit and the second precharge circuit are coupled in parallel to the bit line (node SO is a common node that ultimately connects the three circuit branches that include P102, P103, and the bit lines. Examiner notes that the “parallel” connection of the present application is not actually parallel, but is a roughly parallel configuration, see Fig. 9 of the present application).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ju to modified Lee wherein a memory device comprises a page buffer configured to generate a latch signal based on program data and a voltage level of a sensing node, which is coupled to the bit line, and configured to precharge the bit line responsive to at least one of the bit line precharge signal and the latch signal, wherein the page buffer comprises a first precharge circuit configured to apply a core voltage to the bit line responsive to the bit line precharge signal; second precharge circuit configured to apply the core voltage to the bit line responsive to the latch signal; and a sensing latch circuit configured to generate the latch signal responsive to the voltage level of the sensing node, wherein the first precharge circuit and the second precharge circuit are coupled in parallel to the bit line in order to reduce verification time by including a main latch and a cache latch in the same page buffer (Ju, [0031]).
Regarding claim 5, Lee and Ju together disclose the limitations of claim 4, and further through Ju:
wherein the page buffer (Fig. 1) further comprises a data latch circuit (cache latch 120; [0024]) configured to change the voltage level of the sensing node responsive to the program data ([0025]: The cache latch 120 stores externally input data in connection with programming. A NMOS transistor N112 is driven according to a voltage level of the node S0…NMOS transistors N109 and N110 are driven according to a signal DI1, which becomes active when data received from an I/O pad YA are logical "1" upon programming…A NMOS transistor N111 is driven according to a signal nDI, which becomes active when data received from the I/O pad YA are logical "0" upon programming).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ju to modified Lee wherein a the page buffer further comprises a data latch circuit configured to change the voltage level of the sensing node responsive to the program data in order to reduce verification time by including a main latch and a cache latch in the same page buffer (Ju, [0031]).
Regarding claim 6, Lee and Ju together disclose the limitations of claim 4, and further through Lee:
a verification latch circuit (Fig. 2: C/F register 420; [0114]) configured to change the voltage level of the sensing node responsive to a verification latch signal ([0121]: switch 840 is used to select between two different capacitors... Switch 840 selects between capacitor 842 and 844 based on the value stored in C/F register 420. Examiner asserts that “the value stored in C/F register 420” is a verification latch signal [0097]: During verification, if the memory cell is in the coarse mode, multiplexer 430 will select the coarse time strobe Tc based on C/F register 420. Examiner concludes that the C/F register 420 may be used during verification).
Also, through Ju:
wherein the page buffer (Fig. 1) further comprises a verification latch circuit (P102 and P103) configured to change the voltage level of the sensing node (SO. Examiner asserts that P102 and P103 change the voltage level of SO, however they output verification signals nWDO_ERVER and nWDO_PGMVER instead of being responsive to verification signals)
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ju to modified Lee wherein the page buffer comprises a verification latch circuit configured to change the voltage level of the sensing node in order to reduce verification time by including a main latch and a cache latch in the same page buffer (Ju, [0031]).
Independent claim 13 is nearly identical in claimed subject matter to independent claim 4 and is rejected for the same reasons as independent claim 4.
Regarding claim 14, Lee and Ju together disclose the limitations of claim 13. Claim 14 recites substantially the same limitations as claim 5, and henceforth is rejected for the same reasons.
Regarding claim 15, Lee and Ju together disclose the limitations of claim 13. Claim 15 recites substantially the same limitations as claim 6, and henceforth is rejected for the same reasons.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Dong (US Pub. 20110273935 A1) in view of Mokhlesi (US Pub. 20040156241 A1).
Regarding independent claim 16, Dong discloses a method of operating a memory device (Fig. 3: non-volatile storage device 210; [0053]) comprising a plurality of bit lines ([0197]: a method for operating a non-volatile storage system that includes a plurality of bit lines that are associated with a word line), the operating method comprising:
applying a program voltage ([0081]: program voltage Vpgm) to a plurality of memory cells during a program operation which includes a coarse-program operation and a fine-program operation ([0084]: programming has a coarse mode and a fine mode. In general, a coarse programming mode may attempt to program a memory cell faster when it is further from its target threshold voltage, and program more slowly when the memory cell is closer to its target threshold voltage…The coarse and fine program can also be executed in one program sequence as in FIG. 7B); and
selectively precharging some but not all of the plurality of bit lines to perform a coarse-verification when the program operation is the coarse-program operation ([0089]: FIG. 8A is flowchart of one embodiment of a process 800 for verifying memory cells during a programming process. When verifying the memory cells, certain bias conditions are applied to the bit lines. For example, some bit lines are pre-charged and other [sp] are grounded; [0090]: Process 800 of FIG. 8A may be used during…coarse verify step 756 of FIG. 7C), and
precharging bit lines ([0064]: bit line is charged)
Dong does not disclose:
all the plurality of bit lines to perform a fine-verification when the program operation is the fine-program operation.
However, Mokhlesi teaches:
all the plurality of bit lines to perform a fine-verification when the program operation is the fine-program operation ([0014]: the fine programming phase begins by simultaneously verifying all cells that belong to a programming block against their individual fine programming target thresholds).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Mokhlesi to Dong wherein all the plurality of bit lines perform a fine-verification when the program operation is the fine-program operation in order to reduce the programming current without reducing programming speed (Mokhlesi, [0011]).
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Dong (US Pub. 20110273935 A1) and Mokhlesi (US Pub. 20040156241 A1) as applied to claim 16 above, and further in view of Ju (US Pub. 20060114723 A1).
Regarding claim 17, Dong and Mokhlesi together disclose the limitations of claim 16, and further through Dong:
wherein the selectively precharging a plurality of bit lines ([0089]) is performed responsive to a latch signal ([0141]) stored in a plurality of page buffers, which are respectively coupled to the plurality of bit lines.
Neither Dong nor Mokhlesi discloses a plurality of page buffers.
However, Ju teaches:
a plurality of page buffers ([0029]: a verification signal of a first page buffer group consisting of a plurality of page buffers)
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ju to modified Dong wherein there is a plurality of page buffers in order to reduce verification time by including a main latch and a cache latch in the same page buffer (Ju, [0031]).
Regarding claim 18, Dong, Mokhlesi, and Ju together disclose the limitations of claim 17, and further through Dong:
wherein a logic level of the latch signal is set responsive to program data corresponding to the program voltage and a logic value of a memory cell distribution that is a target of the verification ([0138]: after a memory cell has been programmed to its target threshold voltage, the program data in the data latches 494 is overwritten to indicate that programming is complete. For example, after a memory cell has been programmed to its target threshold voltage, the program data in the data latches is set to the values for the erase state).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Dong (US Pub. 20110273935 A1) and Mokhlesi (US Pub. 20040156241 A1) as applied to claim 16 above, and further in view of Lee (US Pub. 20090010068 A1).
Regarding claim 19, Dong and Mokhlesi together disclose the limitations of claim 16. The first limitation of claim 19 is substantially the same as a combination of the last limitation of claim 16 and part of claim 18.
Neither Dong nor Mokhlesi discloses:
perform the fine-verification when a memory cell distribution, which is a target of the verification, is the same as an established memory cell distribution or a lower memory cell distribution than the established memory cell distribution.
However, Lee teaches:
perform the fine-verification when a memory cell distribution, which is a target of the verification, is the same as an established memory cell distribution ([0065]: At step 364, it is checked whether all of the data latches are storing logic "1." If so, the programming process is complete and successful because all selected memory cells were programmed and verified to their target states; [0070]: Four states are depicted: state E (11), state A (10), state B (00) and state C (01). For state E, both pages store a "1."…Note that although specific bit patterns have been assigned to each of the states, different bit patterns may also be assigned. Examiner concludes that there may be established distributions for different logic states) or a lower memory cell distribution than the established memory cell distribution.
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lee to modified Dong wherein there is a performing of the fine-verification when a memory cell distribution, which is a target of the verification, is the same as an established memory cell distribution or a lower memory cell distribution than the established memory cell distribution in order to provide a page buffer that can verify prior to erasing (Lee, [0001]).
Regarding claim 20, Dong and Mokhlesi together disclose the limitations of claim 16. The first part of claim 20 is substantially the same as the first part of claim 19.
Neither Dong nor Mokhlesi discloses:
selectively precharging the plurality of bit lines to perform the fine-verification when a memory cell distribution, which is a target of the verification, is a higher memory cell distribution than an established memory cell distribution.
However, Lee teaches:
wherein performing the fine-verification when the program operation is the fine-program operation ([0080]) comprises selectively precharging the plurality of bit lines to perform the fine-verification when a memory cell distribution, which is a target of the verification, is a higher memory cell distribution than an established memory cell distribution ([0086]: The dotted line 452 in FIG. 15 represents a memory cell having a threshold voltage below the final verify level V.sub.v2 but above the coarse verify level V.sub.v1. Such a memory cell will not cause discharge with the coarse verify level applied, but will discharge the bit line when the final verify level is applied. The bit line voltage of these memory cells will discharge from the pre-charge level to about 0.5V or lower during the fine level verification. Examiner concludes that the coarse verify level V.sub.v1 may be an established memory cell distribution).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lee to modified Dong wherein selectively precharging the plurality of bit lines to perform the fine-verification when a memory cell distribution, which is a target of the verification, is a higher memory cell distribution than an established memory cell distribution in order to provide a page buffer that can verify prior to erasing (Lee, [0001]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIZABETH ROSE AGGER whose telephone number is (571)270-0250. The examiner can normally be reached Mon-Fri, 8am-5pm.
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/E.R.A./Examiner, Art Unit 2824 /HAN YANG/Primary Examiner, Art Unit 2824
5/30/2026
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