The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by TAKAHASHI et al. (U.S. Patent Application Publication 2016/0240476, hereinafter referred to as TAKAHASHI).
As to claim 1, TAKAHASHI teaches 1. A semiconductor device comprising: a peripheral circuit; a stack that is disposed over the peripheral circuit, the stack comprising alternately stacked insulating layers and sacrificial layers; a first contact structure penetrating through the stack to connect with the peripheral circuit, the first contact structure comprising a protruding part extending outward from a sidewall of the first contact structure; and a second contact structure disposed on the first contact structure, wherein the second contact structure is connected to the protruding part of the first contact structure. [see 104, 91, 8A, 8G, 76, 32, 42 in Fig. 15A for example]
As to claim 2, TAKAHASHI teaches 2. The semiconductor device of claim 1, further comprising: a gate structure comprising conductive layers and the insulating layers that are alternately stacked; channel structures extending through the gate structure [¶0036 for example]; a first interlayer insulating layer disposed on the gate structure; and third contact structures [see 100 in Fig. 15A for example] connected to the channel structures through the first interlayer insulating layer, the third contact structures having upper surfaces disposed at substantially a same level with an upper surface of the protruding part of the first contact structure. [see 100 and 200 in Fig. 15A]
As to claim 6, TAKAHASHI teaches 6. The semiconductor device of claim 1, further comprising a bit line electrically connected to the peripheral circuit through the second contact structure and the first contact structure. [¶0104]
As to claim 7, TAKAHASHI teaches 7. A semiconductor device comprising: a gate structure comprising alternately stacked conductive layers and insulating layers; real channel structures extending through the gate structure; a stack comprising alternately stacked sacrificial layers and insulating layers; a first interlayer insulating layer disposed on the gate structure and the stack; a second interlayer insulating layer disposed on the first interlayer insulating layer; a first contact structure that extends through the first interlayer insulating layer and the stack, the first contact structure comprising a protruding part extending outward from a sidewall of the first contact structure; a second contact structure connected to the protruding part of the first contact structure through the second interlayer insulating layer; and third contact structures connected to the real channel structures through the first interlayer insulating layer. [see 104, 91, 8A, 8G, 76, 32, 42 in Fig. 15A for example]
As to claim 8, TAKAHASHI teaches 8. The semiconductor device of claim 7, further comprising: fourth contact structures connected to the third contact structures, respectively, through the second interlayer insulating layer; and a bit line connected to the first contact structure through the second contact structure and connected to the channel structures through the fourth contact structures and the third contact structures. [see 100 and 200 in Fig. 15A]
As to claim 9, TAKAHASHI teaches 9. The semiconductor device of claim 8, further comprising a peripheral circuit electrically connected to the bit line through the first contact structure and the second contact structure. [¶0104]
As to claim 10, TAKAHASHI teaches 10. The semiconductor device of claim 7, wherein an upper surface of the protruding part of the first contact structure and upper surfaces of the third contact structures are disposed at substantially a same level. [see 100 and 200 in Fig. 15A]
Claim Rejections - 35 USC § 103
1. The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
2. Claim 3-5 rejected under 35 U.S.C. 103(a) as being unpatentable over TAKAHASHI in view of TAKAKI et al. (U.S. Patent Application Publication 2022/0139946, hereinafter referred to as TAKAKI).
As to claim 3, TAKAHASHI teaches 3. The semiconductor device of claim 2, wherein: the channel structures comprise real channel structures, and the third contact structures are connected to the real channel structures. [¶0130]
TAKAHASHI may not explicitly teach dummy channel structures.
TAKAKI teaches this limitation. [¶0043]
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to combine the teachings of TAKAHASHI and TAKAKI to “include dummy channel structures " in TAKAHASHI according to TAKAKI. The Examiner notes that it is well known method of obtaining pattern uniformity by incorporating dummy structures.
As to claim 4, TAKAHASHI and TAKAKI teaches 4. The semiconductor device of claim 3, further comprising: a second interlayer insulating layer disposed on the first interlayer insulating layer; and fourth contact structures connected to the third contact structures, respectively, through the second interlayer insulating layer. [see 100 and 200 in Fig. 15A TAKAHASHI]
As to claim 5, TAKAHASHI and TAKAKI teaches 5. The semiconductor device of claim 4, further comprising a bit line connected to the real channel structures through the fourth contact structures and the third contact structures. [¶0104 TAKAHASHI]
Conclusion
Claims 1-10 are rejected as explained above.
The prior art made of record in the PTO-892 form and not relied upon is considered pertinent to applicant's disclosure.
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/JAEHWAN OH/
Primary Examiner, Art Unit 2899