Prosecution Insights
Last updated: August 17, 2026
Application No. 18/346,674

SEMICONDUCTOR DIE STACK STRUCTURE

Non-Final OA §103
Filed
Jul 03, 2023
Priority
Dec 05, 2022 — RE 10-2022-0167494
Examiner
VALENZUELA, PATRICIA D
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
647 granted / 717 resolved
+22.2% vs TC avg
Minimal +2% lift
Without
With
+2.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
77 currently pending
Career history
797
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
66.4%
+26.4% vs TC avg
§102
16.9%
-23.1% vs TC avg
§112
6.7%
-33.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 717 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 1, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-13, 21-27 in the reply filed on 05/06/26 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-13, 21-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Makabe(USPGPUB DOCUMENT: 2022/0059418, hereinafter Makabe) in view of Chang (USPGPUB DOCUMENT: 2022/0139851, hereinafter Chang). Re claim 1 Makabe discloses a semiconductor die stack structure comprising: a base die(10); a plurality of semiconductor die stack units stacked over the base die(10); and bumps(31B) between the base die(10) and the plurality of semiconductor die stack units and between the plurality of semiconductor dies stack units, wherein each of the plurality of semiconductor die stack units includes a lower semiconductor die(21/23/25) and an upper semiconductor die(22/24/26) stacked over the lower semiconductor die(21/23/25), wherein each of the lower semiconductor die(21/23/25) and the upper semiconductor die(22/24/26) includes: body having a front-side and a back-side; and a third front-side pad portion(31C/30) under the first front-side pad portion(31C/30), wherein the first front-side pad portion(31C/30) and the third front-side pad portion(31C/30) form a reverse staircase (since 31C/30 form bottom steps this may be interpreted as a reverse staircase), wherein the first front-side pad portion(31C/30), the second front-side pad portion, and the third front-side pad portion(31C/30) include a same metal. Makabe does not discloses a front-side pad structure disposed over the front-side of the body, wherein the front-side pad structure includes: a front-side pad seed layer; and a front-side pad pattern over the front-side pad seed layer, wherein the front-side pad pattern includes: a first front-side pad portion(31C/30) having a plate shape; a second front-side pad portion over the first front-side pad portion(31C/30), wherein the first front-side pad portion(31C/30) and the second front- side pad portion forms a staircase; and Chang discloses a front-side pad structure disposed over the front-side of the body, wherein the front-side pad structure includes: a front-side pad seed layer (320/420)[0038]; and a front-side pad pattern over the front-side pad seed layer, wherein the front-side pad pattern includes: a first front-side pad portion(122/123) having a plate shape; a second front-side pad portion over the first front-side pad portion(122/123), wherein the first front-side pad portion(122/123) and the second front- side pad portion forms a staircase(since 122/123 form steps this may be interpreted as a staircase); and It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Chang to the teachings of Makabe in order to minimize reliability issues [0022, Chang]. Re claim 2 Makabe and Chang disclose the semiconductor die stack structure of claim 1, wherein each of the lower semiconductor die(21/23/25) and the upper semiconductor die(22/24/26) further comprises: a back-side passivation layer under the back-side of the body; and a back-side pad structure under the back-side passivation layer, wherein the back-side pad structure includes a back-side pad seed layer under the back-side of the body, and a back-side pad pattern[0011] 1under a lower surface of the back-side pad seed layer (320/420)[0038of Chang], wherein the back-side pad pattern[0011] includes: a first back-side pad portion having a plate shape; and a second back-side pad portion under the first back-side pad portion, wherein the first back-side pad portion and the second back- side pad portion form a reverse staircase, wherein the first back-side pad portion, the second back-side pad portion include a same metal. Re claim 3 Makabe and Chang disclose the semiconductor die stack structure of claim 2, wherein each of the lower semiconductor die(21/23/25) and the upper semiconductor die(22/24/26) further comprises: a back-side pad liner layer conformally surrounding a side surface and a lower surface of the first back-side pad portion and a side surface of the second back-side pad portion; and a back-side bonding insulating layer under the back-side pad liner layer, wherein a lower surface of the second back-side pad portion, a lower end of the back-side pad liner layer, and a lower surface of the back-side bonding insulating layer are co-planar. Re claim 4 Makabe and Chang disclose the semiconductor die stack structure of claim 3, wherein: a width(see Fig 2 of Chang) of the second front-side pad portion is different from a width(see Fig 2 of Chang) of the second back-side pad portion in a first horizontal direction, 1and a width(see Fig 2 of Chang) of the second front-side pad portion is different from a width(see Fig 2 of Chang) of the second back-side pad portion in a second horizontal direction, wherein the first horizontal direction and the second horizontal =~ direction are perpendicular with each other. Re claim 5 Makabe and Chang disclose the semiconductor die stack structure of claim 3, wherein: the second front-side pad portion of the lower semiconductor die(21/23/25) is directly in contact with and bonded to the second back-side pad portion of the upper semiconductor die(22/24/26), and the front-side bonding insulating layer of the lower semiconductor die(21/23/25) is directly in contact with and bonded to the back-side bonding insulating layer of the upper semiconductor die(22/24/26). Re claim 6 Makabe and Chang disclose the semiconductor die stack structure of claim 2, wherein each of the lower semiconductor die(21/23/25) and the upper semiconductor die(22/24/26) further comprises: a top metal pattern disposed in the body to be adjacent to the ‘front-side of the body; and a front-side passivation layer over the front-side of the body to expose an upper surface of the top metal pattern. Re claim 7 Makabe and Chang disclose the semiconductor die stack structure of claim , 1wherein the front-side pad seed layer (320/420)[0038of Chang] includes: a first-side pad seed portion disposed over an upper surface of the front-side passivation; a second front-side pad seed portion disposed over a side surface of the front-side passivation layer; and a third front-side pad seed portion disposed over the exposed upper surface of the top metal pattern. Re claim 8 Makabe and Chang disclose the semiconductor die stack structure of claim , wherein each of the lower semiconductor die(21/23/25) and the upper semiconductor die further comprises: a front-side pad liner layer conformally surrounding a side surface and an upper surface of the first front-side pad portion(31C/30) and a side surface of the second front-side pad portion; and a front-side bonding insulating layer over the front-side pad liner layer, wherein an upper surface of the second front-side pad portion, an upper end of the front-side pad liner layer, and an upper surface of the front-side bonding insulating layer are co-planar. Re claim 9 Makabe and Chang disclose the semiconductor die stack structure of claim , wherein each of the lower semiconductor die(21/23/25) and the upper semiconductor die(22/24/26) further comprises a through-via[0024of Chang] passing through the body to electrically connect the top metal pattern to the back-side pad 1structure. Re claim 10 Makabe and Chang disclose the semiconductor die stack structure of claim 9, wherein each of the lower semiconductor die(21/23/25) and the upper semiconductor die(22/24/26) further comprises: a dummy[0031of Chang] front-side pad structure disposed over the front-side of the body, wherein the dummy[0031of Chang] front-side pad structure is not electrically connected to the through-via[0024of Chang], wherein the dummy[0031of Chang] front-side pad structure includes: a dummy[0031of Chang] front-side pad seed layer (320/420)[0038of Chang]; and a dummy[0031of Chang] front-side pad pattern[0011] over the dummy[0031of Chang] front-side pad seed layer (320/420)[0038of Chang], wherein the dummy[0031of Chang] front-side pad pattern[0011] includes: a first dummy[0031of Chang] front-side pad portion having a plate shape; a second dummy[0031of Chang] front-side pad portion over the first dummy[0031of Chang] front-side pad portion, wherein the first dummy[0031of Chang] front-side pad portion and the second dummy[0031of Chang] front-side pad portion form a staircase; and a third dummy[0031of Chang] front-side pad portion under the first dummy[0031of Chang] front-side pad portion, wherein the first dummy[0031of Chang] front-side pad portion and the third dummy[0031of Chang] front-side pad portion form a reverse staircase, wherein the first dummy[0031of Chang] front-side pad portion, the second dummy[0031of Chang] front-side pad portion, the third dummy[0031of Chang] front-side pad portion includes a same metal. Re claim 11 Makabe and Chang disclose the semiconductor die stack structure of claim , wherein each of the lower semiconductor die(21/23/25) and the upper semiconductor die(22/24/26) further comprises: a dummy[0031of Chang] back-side pad structure under the back-side passivation layer, wherein the dummy[0031of Chang] back-side pad structure is not electrically connected to the through-via[0024of Chang], wherein the dummy[0031of Chang] back-side pad structure includes: a dummy[0031of Chang] back-side pad seed layer (320/420)[0038of Chang] over the back-side of the body; and a dummy[0031of Chang] back-side pad pattern[0011] under the dummy[0031of Chang] back-side pad seed layer, wherein the dummy[0031of Chang] back-side pad pattern[0011] includes: a first dummy[0031of Chang] back-side pad portion having a plate shape; and a second dummy[0031of Chang] back-side pad portion under the first dummy[0031of Chang] back-side pad portion, wherein the first dummy[0031of Chang] back-side pad portion and the second dummy[0031of Chang] back-side pad portion form a reverse staircase, wherein the first dummy[0031of Chang] back-side pad portion and the second back-side pad portion include a same metal. Re claim 12 Makabe and Chang disclose the semiconductor die of stack structure claim 9, wherein: the front-side pad structure includes a signal front-side pad structure and a power front-side pad structure; the back-side pad structure includes a signal back-side pad structure and a power back-side pad structure, 1the top metal pattern includes a signal top metal patten and a power top metal pattern, the through-via[0024of Chang] includes a signal through-via[0024of Chang] and a power through-via[0024of Chang], and the power through-via[0024of Chang] includes a plurality of unit power through- ~-vias electrically and commonly connecting the power top metal pattern to the power back-side pad structure. Re claim 13 Makabe and Chang disclose the semiconductor die stack structure of claim 1, further comprising: heat dissipation molding layers disposed between the base die(10) and the plurality of semiconductor die stack units and between the plurality of semiconductor die stack units, wherein the heat dissipation molding layers surround side surfaces of the bumps(31B), wherein each of the bumps(31B) includes a soler ball, wherein each of the heat dissipation molding layers includes an epoxy resin and aluminum fillers. Re claim 21 Makabe and Chang disclose the semiconductor die stack structure of claim 1, wherein in a top view, the first front-side pad portion(31C/30) and the second front-side pad portion each have a circular shape or a polygonal shape. Re claim 22 Makabe and Chang disclose the semiconductor die stack structure of claim 1, wherein the front-side pad pattern[0011] is arranged with a first horizontal pitch, wherein a horizontal width(see Fig 2 of Chang) of the first front-side pad portion(31C/30) is in a range of 60% to 90% of the first horizontal pitch, and a horizontal width(see Fig 2 of Chang) of the second front-side pad portion is in a range of 20% to 60% of the first horizontal pitch. Re claim 23 Makabe and Chang disclose the semiconductor die stack structure of claim 1, wherein each of the lower semiconductor die(21/23/25) and the upper semiconductor die(22/24/26) further comprises: a dummy[0031of Chang] front-side pad structure disposed over the front-side of the body, wherein the dummy[0031of Chang] front-side pad structure is electrically isolated from through- vias in the body, wherein the dummy[0031of Chang] front-side pad structure includes: a dummy[0031of Chang] front-side pad seed layer (320/420)[0038of Chang]; and a dummy[0031of Chang] front-side pad pattern[0011] over the dummy[0031of Chang] front-side pad seed layer (320/420)[0038of Chang], wherein the dummy[0031of Chang] front-side pad pattern[0011] includes a first dummy[0031of Chang] front- side pad portion having a plate shape, and a second dummy[0031of Chang] front-side padportion over the first dummy[0031of Chang] front-side pad portion, wherein the first dummy[0031of Chang] front-side pad portion and the second dummy[0031of Chang] front-side pad portion form a staircase. Re claim 24 Makabe and Chang disclose the semiconductor die stack structure of claim 1, further comprising a signal through-via[0024of Chang] and a power through-via[0024of Chang] disposed in the body, wherein the front-side pad structure includes a signal front-side pad structure connected to the signal through-via[0024of Chang] and a power front-side pad structure connected to the power through-via[0024of Chang], wherein the power through-via[0024of Chang] includes a plurality of unit power through- vias electrically and commonly connected to the power front-side pad structure. Re claim 25 Makabe and Chang disclose the semiconductor die stack structure of claim 1, wherein the second front-side pad portion has an elongated bar shape(see Fig 2 of Chang) extending in a first horizontal direction. Re claim 26 Makabe and Chang disclose the semiconductor die stack structure of The semiconductor die stack structure of wherein the second front-side pad portion of the lower semiconductor die(21/23/25) is directly in contact with and bonded to the second front-side pad portion of the upper semiconductor die(22/24/26). Re claim 27 Makabe and Chang disclose the semiconductor die stack structure of claim 1, further comprising a heat dissipation molding layer disposed on side surfaces of the plurality of semiconductor die stack units(see Fig 2 of Chang), wherein the heat dissipation molding layer includes an epoxy resin and aluminum nitride fillers. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jul 03, 2023
Application Filed
Jul 30, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+2.1%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 717 resolved cases by this examiner. Grant probability derived from career allowance rate.

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