Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed May 22, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 10, 13
b. Pending: 1-20
Claims 1, 10, 13, and 18 have been amended.
Claim Objections
The claim objection is withdrawn pursuant to claim amendments.
Response to Arguments
Applicant's arguments filed May 22, 2026 have been fully considered but they are not persuasive. Examiner acknowledges that, per the arguments on p.13, You (US Pub. 20200233770 A1) does not disclose sensing states in a plurality of memory blocks, as You only senses states in a selected block. However, per the revised rejection of claim 1 below, Kumazaki (US Pub. 20220406351 A1) teaches sensing states in a plurality of memory blocks.
Regarding the following argument against Kumazaki on p.14:
“Thus, the parallel read operations of Kumazaki are directed to performing read operations in parallel in a plurality of planes by using respective bit lines and respective sense amplifier modules. Namely, Kumazaki does not disclose or suggest the configuration of amended claims, in which each of the sensed states is determined according to operations of target select transistors that are respectively included in the plurality of memory blocks and coupled to a corresponding bit line among the bit lines.”
This is argument is not persuasive because the claim language “each of the sensed states is determined according to operations…of target select transistors” is broad enough such that Kumazaki indeed teaches it. Kumazaki teaches select transistors within memory blocks (paras. [0060]-[0061]), and per para. [0151], these select transistors are crucial to a read operation, which per para. [0155] senses the state of the memory cells in the block.
Regarding the statement on p.14 that Chen et al. (US Pub. 20160358662 A1; “Chen”) “fails to remedy the above deficiencies of You and Kumazaki”:
Chen, like Kumazaki, teaches select transistors (paras. [0041]-[0043]) and multiple sub-blocks sharing a bit line ([0043]). Also, per para. [0106], “the select gate lines can be connected and commonly controlled”, meaning that operations, such as sensing operations, may be performed in multiple blocks or regions in parallel. Thus, Kumazaki and Chen both remedy the deficiencies of You.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 10, and 13 recite the limitation "target select transistors" in the penultimate line of claim 1 on p.2, in the penultimate line of claim 10 on p.5, and on the second line of p.7, respectively. There is insufficient antecedent basis for this limitation in the claim. Examiner suspects that “target select transistors” should be changed to “the plurality of target select transistors”. Independent claims 1, 10, and 13, and claims 2-9, 11-12, and 14-20, which depend on the independent claims, are thus rejected under 35 U.S.C. 112(b).
Also, claims 1, 10, and 13 all recite “…is determined according to operations” in the third from last line of claim 1 on p.2, in the third from last line of claim 10 on p.5, and in the first two lines of p.7, respectively. The word “operations” is indefinite because it is broad and could encompass any operation, such as erase, program, or write. There is no support in the Specification for determining “sensed states” (claims 1 and 13) or “read-values” (claim 10) according to erase, program, or write operations of target select transistors.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-7, 9-10, 12-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over You (US Pub. 20200233770 A1) in view of Kumazaki (US Pub. 20220406351 A1).
Regarding independent claim 1, You discloses a memory device (Fig. 3: memory device MD; [0058]) comprising:
a plurality of memory blocks (Fig. 4: memory blocks MB1 to MBk; [0066]: Referring to FIG. 4, the memory cell array 110 may include a plurality of planes…Each of the first to ith planes P1 to Pi may include a plurality of memory blocks), each including a plurality of target select transistors (Fig. 6: source select transistor SST and drain select transistor DST; [0073]) respectively coupled to a plurality of target select lines ([0074]: The source select transistors SST of cell strings arranged in the same row may be coupled to the same source select line (SSL1 or SSL2); [0076]: The drain select transistors DST of the cell strings ST11′ to ST1m′ arranged in the first row may be coupled to a first drain select line DSL1); and
a peripheral circuit (Fig. 1: memory controller 1200; [0042]) configured to check a shift in threshold voltages of the plurality of target select transistors (Fig. 21: steps S21, S26, S31, and S36; [0174]: The memory system may check a left threshold voltage Vth of the drain select transistor DST included in an Nth cell string of the selected memory block by using the first check command set (S21); also see [0178], [0182], and [0186]) by applying, through a plurality of global select lines respectively coupled to the plurality of target select lines of each of the plurality of memory blocks and connected to the plurality of memory blocks in response to activation of selection signals respectively corresponding to the plurality of memory blocks (per a description of step S21 of Fig. 21, [0174] discloses: the memory controller may output the first check command set. The memory device may read the drain select transistor DST included in the Nth cell string, among a plurality of cell strings included in the selected memory block, and may output the read information to the memory controller in response to the first check command set; [0108]: The central processing unit 220 may output a check command set CHK_CMDs for checking threshold voltages of select transistors of a selected memory block in response to the trigger signal TGS. The check command set CHK_CMDs may include a read command and an address of select transistors. Examiner asserts that the drain select transistor DST is connected to a drain select line DSL per [0076], and DSL is analogous to a global select line. The Nth cell string is analogous to the target select line, and the first check command set is analogous to a selection signal), a reference voltage generated by a voltage-supply circuit (Fig. 3: voltage generator 120; [0058]; [0151]: Referring to FIG. 19, a memory device…may set reference voltages for checking threshold voltages of select transistors in response to a setup command (S190)) to the plurality of target select transistors respectively ([0124]: Referring to FIG. 13, a left reference voltage Vl and a right reference voltage Vr may be set to check whether threshold voltages Vth of drain and source select transistors are shifted), and
You does not explicitly disclose:
concurrently check threshold voltages of the plurality of target select transistors by simultaneously applying a reference voltage
by sensing states of bit lines commonly coupled to the plurality of memory blocks to determine the shift based on the sensed states,
wherein each of the sensed states is determined according to operations, in response to the reference voltage, of target select transistors that are respectively included in the plurality of memory blocks and coupled to a corresponding bit line among the bit lines.
However, Kumazaki teaches:
concurrently check threshold voltages of the plurality of target select transistors by simultaneously applying a reference voltage ([0224]: In the memory die MD′, there is a case where the read operation or the like is simultaneously or concurrently executed on the plurality of memory planes MP; [0144]: At timing t101 of the read operation, the read pass voltage V.sub.READ is applied…A voltage V.sub.SG is applied to the select gate lines (SGD, SGS, SGSb). The voltage V.sub.SG has a magnitude enough to form electron channels in the channel regions of the select transistors (STD, STS, STSb) , thereby causing the select transistors (STD, STS, STSb) to be in the ON state. Examiner concludes that multiple target select transistors may be read at once, thus the threshold voltages of those transistors are checked, and also the reading involves applying a read reference voltage)
by sensing states of bit lines (per [0141], Fig. 14 describes the read operation, which is analogous to a sensing operation; [0147]: At timing t102, for example, a voltage V.sub.DD is applied to the bit lines BL) commonly coupled to the plurality of memory blocks (per Fig. 5, bit lines BL are commonly coupled to three blocks BLK) to determine the shift based on the sensed states ([0155]: in the read operation, arithmetic processing, such as AND and OR, is executed on the data indicative of the state of the above-described memory cell MC, and this calculates the data stored in the memory cell MC; [0062]: The memory cell MC has a threshold voltage that changes according to an electric charge amount in the electric charge accumulating film),
wherein each of the sensed states ([0155]) is determined according to operations ([0151]: read operation), in response to the reference voltage, of target select transistors ([0151]: The voltage V.sub.SG is applied to the select gate lines (SGD, SGS, SGSb) to cause the select transistors (STD, STS, STSb) to be in the ON state) that are respectively included in the plurality of memory blocks and coupled to a corresponding bit line among the bit lines (see Fig. 5).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kumazaki to You wherein the memory device is configured to concurrently check threshold voltages of the plurality of target select transistors by simultaneously applying a reference voltage; and by sensing states of bit lines commonly coupled to the plurality of memory blocks to determine the shift based on the sensed states, wherein each of the sensed states is determined according to operations, in response to the reference voltage, of target select transistors that are respectively included in the plurality of memory blocks and coupled to a corresponding bit line among the bit lines in order to reduce the effects of leakage current on the voltage supply lines (Kumazaki, [0230]).
Regarding claim 2, You and Kumazaki together disclose the limitations of claim 1, and further through You:
wherein the peripheral circuit (Fig. 1: 1200) checks the shift (Fig. 21: S21, S26, S31, and S36; [0174]) further by:
applying a pass voltage to word lines and select lines that are coupled to strings, to which the plurality of target select lines are coupled ([0070]: The cell strings ST may further include vertical channel layers CH and the bit lines BL. The vertical channel layers CH may vertically pass through the source select lines SSL, the word lines WL and the drain select lines DSL), and
applying a non-selection voltage to select lines, to which the pass voltage has not been applied ([0006]: The drain select transistor may electrically couple or decouple the bit line and the memory cells, and the source select transistor may electrically couple or block the source line and the memory cells; [0060]: pass voltage. Examiner asserts that memory cells in word lines and select lines are either coupled or blocked but not both, and that a voltage must be applied to the memory cells to couple or block them from an operation).
Regarding claim 4, You and Kumazaki together disclose the limitations of claim 1, and further through You:
wherein the peripheral circuit (Fig. 1: 1200) determines read values respectively corresponding to the sensed states of the bit lines commonly coupled to the plurality of memory blocks and checks the shift based on the read values ([0152]: the threshold voltages of the select transistors may be checked through a read operation. To perform the read operation, since some of the latches included in the page buffers may be necessarily initialized, the memory device may initialize some of the latches included in the page buffers; [0153]: the selected memory device may check the threshold voltages Vth of the drain and source select transistors DST and SST included in the selected memory block according to the received check command set (S192). Information about the checked threshold voltages may be output as status information to the memory controller and stored in the memory controller; [0154]: Based on the status information stored in the memory controller, threshold voltage (Vth) shifts of the drain and source select transistors DST and SST of the selected memory block may be determined (S193)).
Regarding claim 5, You and Kumazaki together disclose the limitations of claim 4, and further through You:
wherein the peripheral circuit (Fig. 1: 1200) senses each of the states based on a number of target select transistors which are turned on in response to the reference voltage among target select transistors coupled to a corresponding bit line and a number of target select transistors which are turned off in response to the reference voltage among the target select transistors coupled to the corresponding bit line (Examiner notes that while the prior art does not mention on or off states, we know that when a select transistor shifts in threshold voltage, this could cause the transistor to turn off. [0104]: The status monitor 52 may output status signals based on the number of select transistors having a changed threshold voltage as indicated by the status information STIF; [0103]: The status information register 51 may store and update status information STIF received from a memory device. The status information STIF may correspond to information about threshold voltages of select transistors; [0048]: the memory controller 1200 may include an error correction component (ECC) 210, a central processing unit 220, an internal memory 230, a memory interface 240, a status manager 250; Fig. 16 shows fail bit counters, which count the number of select transistors that are off, which indicates that those select transistors had shifted threshold voltages).
Regarding claim 6, You and Kumazaki together disclose the limitations of claim 4, and further through You:
wherein the reference voltage is a left reference voltage when the shift is a left shift, and
wherein the reference voltage is a right reference voltage when the shift is a right shift ([0142]: ‘DST_Left’ may refer to a low level of a threshold voltage distribution of a drain select transistor and ‘Vdlr’ may be set for this value. Vdlr may refer to a voltage for checking a low threshold voltage of the drain select transistor…Vdrr may refer to a voltage for checking a high threshold voltage of the drain select transistor…Vslr may refer to a voltage for checking a low threshold voltage of the source select transistor…Vsrr may refer to a voltage for checking a high threshold voltage of the source select transistor).
Regarding claim 7, You and Kumazaki together disclose the limitations of claim 6, and further through You:
wherein the peripheral circuit (Fig. 1: 1200) checks the shift ([0152]-[0154]) further by:
generating a check current based on the read values ([0099]: the drain select transistor DST may control the amount of current IBL between the bit line BL and the memory cells, and the source select transistor SST may control the amount of current ISL between the source line SL and the memory cells MC), and
comparing the check current and a reference current ([0099]: when threshold voltages of the drain or source select transistors DST or SST are lower than a normal threshold voltage, the amount of current sensed from the memory cells during a sensing operation may be lower than a normal current amount. Examiner asserts that the “normal current amount” is analogous to a reference current), and
generating, based on a result of the comparing, a check signal indicating that the shift exceeds a predetermined threshold ([0100]: changes in threshold voltages of the drain and source select transistors DST and SST as described above may be checked to obtain a check result, status information on the check result may be stored).
Regarding claim 9, You and Kumazaki together disclose the limitations of claim 7, and further through You:
wherein the peripheral circuit (Fig. 1: 1200) compares the check current and the reference current ([0099]) by:
generating, when the shift is the left shift, the reference current based on a left bias signal (Fig. 13: left reference voltage Vl; [0124]. Fig. 13 shows Vl is a voltage limit for left-shifting. The Examiner asserts that the left reference voltage Vl is analogous to a “reference current based on a left bias signal” since per Ohm’s law, V=IR, so a voltage is proportionate to a current) corresponding to a maximum tolerable number of target select transistors having threshold voltages left shifted in the plurality of memory blocks ([0124]: The left reference voltage Vl may be for checking whether a threshold voltage is decreased. Examiner asserts that the broadest reasonable interpretation of “maximum tolerable number of target select transistors” is the number of target select transistors that were used to determine the boundaries of or definition of a shift in select transistor threshold voltage. ), and
generating, when the shift is the right shift, the reference current based on a right bias signal (right reference voltage Vr; [0124]) corresponding to a maximum tolerable number of target select transistors having threshold voltages right shifted in the plurality of memory blocks ([0124]: The right reference voltage Vr may be set to an average voltage of the highest voltage of a threshold voltage distribution of select transistors before threshold voltages are shifted).
Independent claim 10 contains limitations that are the same in claimed subject matter to claims 1 and 4 and therefore those limitations are rejected for the same reasons as independent claim 1 and claim 4.
Regarding claim 12, You and Kumazaki together disclose the limitations of claim 10, and further through You:
wherein the peripheral circuit (Fig. 1: 1200) reads the read-values from the respective bit lines by applying a second reference voltage to the plurality of target select transistors ([0124]: Referring to FIG. 13, a left reference voltage Vl and a right reference voltage Vr may be set to check whether threshold voltages Vth of drain and source select transistors are shifted…The right reference voltage Vr may be set to an average voltage of the highest voltage of a threshold voltage distribution of select transistors before threshold voltages are shifted), and
wherein the peripheral circuit checks the shift by checking whether the threshold voltages are higher than the second reference voltage based on the read-values ([0125]: when the checked left shift value of the select transistor is ‘0’ and the right shift value is ‘1’, the status monitor 52 may determine that the threshold voltage Vth of the corresponding select transistor is increased).
Independent claim 13 contains a first limitation that is the same in claimed subject matter to independent claim 1 and so the first limitation is rejected for the same reasons as independent claim 1. Further, through You:
a controller configured to control the check operation ([0162]: Referring to FIG. 20, the memory controller may transfer the check command set CHK_CMDs to the selected memory device at step S192 (S200). The check command set CHK_CMDs may include a read command and an address of the select transistors).
Regarding claim 14, You and Kumazaki together disclose the limitations of claim 13. Claim 14 contains limitations that are mostly the same as claims 6 and 14 and thus claim 14 is rejected for the same reasons.
Regarding claim 15, You and Kumazaki together disclose the limitations of claim 13, and further through You:
wherein the controller controls the check operation by setting a left bias signal when the shift is a left shift and a right bias signal when the shift is a right shift ([0120]: Shift values of threshold voltages of drain select transistors of the same order in the same plane may be output as drain codes DC<i:1>, and shift values of threshold voltages of source select transistors may be output as source codes SC<i:1>, where ‘i’ is a positive integer; regarding Fig. 14, per [0129]: the drain codes DC<i:1> and the source codes SC<i:1> corresponding to the left shift values for the first plane P1 may be output as a single group to the status monitor 52, and the drain codes DC<i:1> and the source codes SC<i:1> corresponding to the right shift values for the first plane P1 may be output as another group to the status monitor 52).
Regarding claim 16, You and Kumazaki together disclose all the limitations of claim 13. Claim 16 is mostly same in claimed subject matter as claim 4, and henceforth is rejected for the same reasons.
Regarding claim 17, You and Kumazaki together disclose all the limitations of claim 16. Claim 17 is the same in claimed subject matter as claim 6, and henceforth is rejected for the same reasons.
Regarding claim 18, You and Kumazaki together disclose all the limitations of claim 17. Claim 18 is the same in claimed subject matter as claim 7, and henceforth is rejected for the same reasons.
Regarding claim 20, You and Kumazaki together disclose all the limitations of claim 18. Claim 20 is the same in claimed subject matter as claim 9, and henceforth is rejected for the same reasons.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over You (US Pub. 20200233770 A1) and Kumazaki (US Pub. 20220406351 A1) as applied to claim 2 above, and further in view of Chen (US Pub. 20160358662 A1).
Regarding claim 3, You and Kumazaki together disclose the limitations of claim 2. Neither You nor Kumazaki disclose:
the pass voltage is a high voltage causing tum-on of a memory cell or a select transistor, and
the non-selection voltage is a low voltage causing tum-off of a select transistor.
However, Chen teaches:
the non-selection voltage is a low voltage causing tum-off of a select transistor ([0068]: instructions for ramping down a voltage of a selected source-side select gate line from a respective turn-on voltage, Vsgs_sel_on, to a respective turn-off voltage (165); and instructions for ramping down a voltage of a selected drain-side select gate line from a respective turn-on voltage, Vsgd_sel_on, to a respective turn-off voltage, Vsgd_sel_off (166); per Figs. 10C and 10D, Vsgd_sel_on and Vsgs_sel_on are greater than Vsgd_sel_off and Vsgs_sel_off, respectively. Examiner asserts that Vsgd_sel_on and Vsgs_sel_on are pass voltages and they are higher than Vsgd_sel_off and Vsgs_sel_off, which are non-selection voltages).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Chen to modified You wherein the pass voltage is a high voltage causing tum-on of a memory cell or a select transistor, and the non-selection voltage is a low voltage causing tum-off of a select transistor in order to reduce hot electron injection read disturb by controlling the selected gate and word line voltages (Chen, [0051]).
Allowable Subject Matter
Claims 8, 11, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure:
Kunori et al. (US Pat. 6144584 A): col. 18, lines 29-51, and Figs. 10A-10C
are relevant to claims 1, 10, and 13.
Zhao et al. (US Pub. 20190392894 A1): paras. [0172] & [0184], and Fig. 4D are relevant to claims 1, 10, and 13.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Khamdan N. Alrobaie/ Primary Examiner, Art Unit 2824
/E.R.A./Examiner, Art Unit 2824
8/12/2026
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