The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Election/Restrictions
Applicant’s election of the embodiment of figure 3 in the reply filed on 10/30/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-13, 16, 18 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Bouthinon et al. (2020/0301477) in view of Lee et al. (12,133,927).Regarding claims 7 and 16, Bouthinon et al. teach in figures 1, 2 and related text a display apparatus, comprising:
a substrate 13 (see figure 2), having a first surface and a second surface opposite to each other;
a pixel structure 1, disposed on the first surface of the substrate; and
a back side line 9 (see figure 1), disposed on the second surface of the substrate 13 (since display screen 1 depicted in figure 1 is the display screen 1 depicted in figure 2), and electrically connected to the pixel structure;
a conductive shielding layer 3, disposed between the second surface of the substrate 13 and the back side line 9, and having a DC level.
Bouthinon et al. do not explicitly state that the back side line, is a back side signal line. Lee et al. teach in figure 8 and related text an electronic board comprises a back side signal line 814.
Bouthinon et al. and Lee et al. are analogous art because they are directed to electronic boards and one of ordinary skill in the art would have had a reasonable expectation of success to modify Bouthinon et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the back side line as a back side signal line, as taught by Lee et al., in Bouthinon et al.’s device, in order to enhance the device capabilities.
The combination is motivated by the teachings of Bouthinon et al. who point out that the disclosed device is formed on electronic board 7 which includes “supporting components”.
Regarding claim 8, in the combined device. an insulating layer 730 (in Lee et al.), disposed between the second surface of the substrate 13 and the back side signal line 9 (since electronic board 800 of Lee et al. replaces the electronic board of Bouthinon et al.), wherein the conductive shielding layer 3 is disposed between the second surface of the substrate 13 and the insulating layer 730.
Regarding claim 9, Bouthinon et al. teach in figures 1, 2 and related text that the conductive shielding layer 3 is grounded or electrically connected to a system high voltage terminal.
Regarding claim 10, Bouthinon et al. teach in figures 1, 2 and related text that the conductive shielding layer shields the second surface of the substrate.
Regarding claim11, Bouthinon et al. teach in figures 1, 2 and related text that the conductive shielding layer shields the back side signal line.
Regarding claim 12, Bouthinon et al. teach in figures 1, 2 and related text that the pixel structure 1 comprises a thin film transistor, and the conductive shielding layer 3 shields a gate of the thin film transistor.
Regarding claim 13, Bouthinon et al. teach in figures 1, 2 and related text that the pixel structure 1 further comprises a light emitting component electrically connected to the thin film transistor, and the gate 171 of the thin film transistor shielded by the conductive shielding layer 3, but does not explicitly state that gate is in a floating state when the light emitting component emits light. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the gateto be in a floating state when the light emitting component emits light, in Bouthinon et al.’s device, in order to operate the device in its intended use.
Regarding claim 16, Bouthinon et al. teach in figures 1, 2 and related text that conductive shielding layer 3, located between the pixel structure 1 and the back side signal line 9, and having a DC level.
Regarding claim 18, Bouthinon et al. teach in figures 1, 2 and related text that the conductive shielding layer 3 is grounded or electrically connected to a system high voltage terminal.
Regarding claim 20, Bouthinon et al. teach in figures 1, 2 and related text that the pixel structure 1 comprises a thin film transistor, and the conductive shielding layer shields a gate 171 of the thin film transistor.
Regarding claim 21, Bouthinon et al. teach in figures 1, 2 and related text that the pixel structure 1 further comprises a light emitting component electrically connected to the thin film transistor, and the gate 171 of the thin film transistor shielded by the conductive shielding layer 3 is in a floating state when the light emitting component emits light (as articulated with respect to claim 13 above).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
1/27/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800