DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-14, drawn to a semiconductor integrated circuit, in the reply filed on 10/21/2025 is acknowledged.
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/21/2025.
Specification
The abstract of the disclosure is objected to because minor informalities, star symbols at the bottom of the abstract. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 4-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et. al., U.S. Pat. Pub. 2007/0246843, hereafter Yang.
Regarding claim 1, Yang discloses (Figs. 1,2, par. [0025], [0027]) a semiconductor integrated circuit, comprising:
a substrate [10]; and
an overlay mark structure [220]-[223] and [231]-[234] in the substrate (par. [0038]) and comprising first overlay marks [220], [221], [222], [223] and second overlay marks [231], [232], [233], [234] separated from each other,
wherein a first mark width [d] (200 to 600 nm) of the first overlay marks is smaller than a second mark width [D] (2000 to 4000 nm) of the second overlay marks (par. [0027]).
Regarding claim 4, Yang further discloses (Fig. 2) wherein the second overlay marks [231]-[234] surround the first overlay marks [220]-[223].
Regarding claim 5, Yang further discloses (Fig.2) wherein a first mark distance between adjacent two first overlay marks ([220] and [222]) of the first overlay marks is smaller than a second mark distance between adjacent two second overlay marks ([231] and [233]) of the second overlay marks (see Fig. 2).
Claims 10-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yao et. al., U.S. Pat. Pub, hereafter Yao.
Regarding claim 10, Yao discloses (Figs 3-5) a semiconductor device, comprising:
a first semiconductor integrated circuit [15] comprising a first overlay mark structure [14], [20], wherein the first overlay mark structure comprises a first overlay mark [20] and a second overlay mark [14] separated from each other, a first mark width [w] of the first overlay mark is smaller than a second mark width [W] of the second overlay mark (par. [0032] & [0036]); and
a second semiconductor integrated circuit [17] disposed on the first semiconductor integrated circuit [15] along a first direction [z] and comprising a second overlay mark structure [16], wherein the second overlay mark structure [16] comprises a third overlay mark [16], the third overlay mark at least partially overlaps the first overlay mark [20] of the first semiconductor integrated circuit along the first direction (Figs. 3A,3B).
Regarding claim 11, Yao further discloses wherein a third mark width of the third overlay mark [16] of the second semiconductor integrated circuit [17] is larger than the first mark width [w] of the first overlay mark [20] of the first semiconductor integrated circuit [15] (see Figs 3A-3B).
Regarding claim 12, Yao further discloses (Figs. 3A,3B) wherein the first overlay mark [20] of the first semiconductor integrated circuit [15] directly contacts the third overlay mark [16] of the second semiconductor integrated circuit [17].
Regarding claim 13, Yao further discloses wherein the first semiconductor integrated circuit further comprises a first substrate (e.g., [15] in Figs 2-3, [124] in Figs 4-5), the first overlay mark structure is in the first substrate [15], the second semiconductor integrated circuit further comprises a second substrate [17] (in Figs 2-3), the second overlay mark structure [16] is in the second substrate, and the second overlay mark [20] of the first semiconductor integrated circuit [15] directly contacts the second substrate [17] of the second semiconductor integrated circuit (see Figs 3A, 3B).
Regarding claim 14, Yao further discloses (Figs 3A, 3B) wherein the third overlay mark [16] of the second semiconductor integrated circuit [17] directly contacts the first overlay mark [10] and the first substrate [16] of the first semiconductor integrated circuit.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, U.S. Pat. 6,083,807, hereafter Hsu, in view of Chen et. al., U. S. Pat. 10,504,852, hereafter Chen.
Regarding claim 1, Hsu discloses a semiconductor alignment mark structure, comprising:
a substrate (abstract, line 5, not shown in the drawings); and
an overlay mark structure [61]-[68] in the substrate and comprising first overlay marks [61b],[62b] and second overlay marks [65],[66] separated from each other,
wherein a first mark width (0.2 um to 0.3 um, claim 2) of the first overlay marks is smaller than a second mark width (1 um to 3 um, claim 3) of the second overlay marks.
Hsu fails to explicitly disclose a semiconductor integrated circuit comprising a semiconductor alignment mark
However, Chen discloses (title, Fig. 1) a semiconductor integrated circuit comprising a semiconductor alignment mark [AM1], [AM2].
It would have been obvious to one having ordinary skill in the art prior to effective date of the instant application to utilize the alignment marks of Hsu to align integrated circuits as taught by Chen, because optical overlay marks such as those of Hsu result in a precise alignment and because Chen teaches (Figs 1, 16) that the integrated circuits in dies [100] and [200] can be aligned by overlay marks [AM1], [AM2]
Regarding claim 2, Hsu in view of Chen discloses everything as applied above. Hsu further discloses (Fig. 6) wherein the first overlay marks [61b],[62b] surround the second overlay marks [65],[66].
Regarding claim 3, Hsu in view of Chen discloses everything as applied above. Hsu further discloses (Fig. 6) wherein a first mark distance between adjacent two first overlay marks (between [61b] and [62b]) of the first overlay marks is larger than a second mark distance between adjacent two second overlay marks (between [65] and [66]) of the second overlay marks [65],[66].
Allowable Subject Matter
Claims 6-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 6, the prior art of record fails to explicitly disclose or make obvious:
wherein the overlay mark structure further comprises third overlay marks separated from each other, a third mark width of the third overlay marks is smaller than the second mark width of the second overlay marks,
the first overlay marks are arranged along a first direction, the second overlay marks are arranged along the first direction, the third overlay marks are arranged along the first direction,
the second overlay marks are between the first overlay marks and the third overlay marks.
Regarding claim 8, the prior art of record fails to explicitly disclose or make obvious:
the overlay mark structure further comprises fifth overlay marks separated from each other, the first mark width of the first overlay marks is smaller than a fifth mark width of the fifth overlay marks,
the first overlay marks are arranged along a first direction, the second overlay marks are arranged along the first direction, the fifth overlay marks are arranged along the first direction,
the first overlay marks are between the second overlay marks and the fifth overlay marks.
Claims 7 and 9 include allowable subject matter of respective claims 6 and 8 they depend upon.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR V BARZYKIN whose telephone number is (571)272-0508. The examiner can normally be reached Monday-Friday, 9am-5pm.
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/VICTOR V BARZYKIN/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893