Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/17/2026 has been entered.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 5, 6 and 25 rejected under 35 U.S.C. 103 as being unpatentable over Fujii (U.S. Patent No. 6,171,881) of record, in view of Fischetti (KR 100232320) of record, in view of Steiner (U.S. Patent No. 6,133,618) of record.
Regarding Claim 1
Fujii discloses a method of forming a microelectronic device, comprising: (FIG. 3) providing a substrate (1) having a top surface; forming a trench (3) in the substrate, the trench extending into the substrate from the top surface; forming a dielectric material layer (5) in the trench (FIG. 4); semi-amorphous polysilicon (6) on the dielectric material layer, the semi-amorphous polysilicon filling the trench (FIG. 5), wherein the semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon (mixture of amorphous and polycrystalline).
Fujii is silent with respect to “forming an amorphous dielectric material layer in the trench” and “heating the substrate to convert the semi-amorphous polysilicon to a polysilicon core contacting the amorphous dielectric material layer and filling the trench”.
FIG. 12 of Fischetti discloses a similar method of forming a microelectronic device, comprising heating the substrate to convert the semi-amorphous polysilicon to a polysilicon core (153) contacting the dielectric material layer and filling the trench (142).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the method of Fujii, as taught by Fischetti. The ordinary artisan would have been motivated to modify Fujii in the above manner for purpose of growing silicon grains.
Fujii as modified by Fischetti is silent with respect to “forming an amorphous dielectric material layer in the trench”.
However, Fujii discloses forming a silicon dioxide layer (5) in the trench, and FIG. 1 of Steiner discloses a similar method of forming a microelectronic device, comprising forming silicon oxide layer (120) in the trench followed with gradual transition from silicon oxide to amorphous dielectric (Col. 2, Lines 55-67).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the method of Fujii, as taught by Steiner. The ordinary artisan would have been motivated to modify Fujii in the above manner for purpose of improving absorbing characteristics and lithography results (Col. 7, Lines 22-25 of Steiner).
Regarding Claim 5
Steiner discloses the amorphous dielectric material is formed by a chemical vapor deposition process (Col. 5, Lines 35-38).
Regarding Claim 6
Fujii discloses the amorphous dielectric material layer (5) includes silicon dioxide, silicon nitride, silicon oxynitride, or a combination thereof.
Regarding Claim 25
FIG. 28 of Fujii discloses the trench extends from the top surface to a polysilicon gate of a transistor of the substrate.
Claim 1 rejected under 35 U.S.C. 103 as being unpatentable over Fujii, in view of Fischetti, in view of Ji (CN 107026206, machine-translation provided).
Regarding Claim 1
Fujii discloses a method of forming a microelectronic device, comprising: (FIG. 3) providing a substrate (1) having a top surface; forming a trench (3) in the substrate, the trench extending into the substrate from the top surface; forming a dielectric material layer (5) in the trench (FIG. 4); semi-amorphous polysilicon (6) on the dielectric material layer, the semi-amorphous polysilicon filling the trench (FIG. 5), wherein the semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon (mixture of amorphous and polycrystalline).
Fujii is silent with respect to “forming an amorphous dielectric material layer in the trench” and “heating the substrate to convert the semi-amorphous polysilicon to a polysilicon core contacting the amorphous dielectric material layer and filling the trench”.
FIG. 12 of Fischetti discloses a similar method of forming a microelectronic device, comprising heating the substrate to convert the semi-amorphous polysilicon to a polysilicon core (153) contacting the dielectric material layer and filling the trench (142).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the method of Fujii, as taught by Fischetti. The ordinary artisan would have been motivated to modify Fujii in the above manner for purpose of growing silicon grains.
Fujii as modified by Fischetti is silent with respect to “forming an amorphous dielectric material layer in the trench”.
FIG. 1 of Ji discloses a similar method of forming a microelectronic device, comprising forming oxide layer (116) in the trench followed with plasma treatment (118) to form amorphous dielectric (116a).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the method of Fujii, as taught by Ji. The ordinary artisan would have been motivated to modify Fujii in the above manner for purpose of blocking leakage current ([0044] of Ji).
Claims 2 and 4 rejected under 35 U.S.C. 103 as being unpatentable over Fujii, Fischetti and Steiner in view of Choi (U.S. Patent No. 6,188,104) of record.
Regarding Claim 2
Fujii as modified by Fischetti and Steiner discloses Claim 1.
With respect to “20 weight percent to 90 weight percent”, said percentage is related to the crystallization (abstract of Choi). Therefore, said percentage is considered to be a result effective variable, where the result is the change in the mobility of the carrier ([0065] of U.S. Patent Pub. No. 2010/0208187 provides documentary evidence). The claim to a specific distance therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05). Furthermore, FIG. 1 of Choi discloses the semi-amorphous polysilicon (26-28) includes 20 weight percent to 90 weight percent of the amorphous silicon pockets.
Regarding Claim 4
Fujii as modified by Fischetti and Steiner discloses Claim 1.
Fujii as modified by Fischetti and Steiner is silent with respect to “the amorphous dielectric material is formed by thermal oxidation of silicon”.
Choi discloses a similar method of forming a microelectronic device, wherein the amorphous dielectric material is formed by thermal oxidation of silicon (Col. 3, Lines 54-56).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Fujii, as taught by Choi. The ordinary artisan would have been motivated to modify Fujii in the above manner for purpose of reducing a leakage current (Col. 1, Lines 6-12 of Choi).
Claim 3 rejected under 35 U.S.C. 103 as being unpatentable over Fujii Fischetti and Steiner, in view of Ibok (U.S. Patent No. 5,930,658) of record.
Regarding Claim 3
Fujii as modified by Fischetti and Steiner discloses Claim 1.
Fujii as modified by Fischetti and Steiner is silent with respect to “the semi-amorphous polysilicon is formed by a chemical vapor deposition process using silane at a temperature of 555 °C to 580 °C”.
Ibok discloses a similar method of forming a microelectronic device, wherein the semi-amorphous polysilicon is formed by a chemical vapor deposition process using silane at a temperature of 555 °C to 580 °C (Col. 6, Lines 16-18).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Fujii, as taught by Ibok. The ordinary artisan would have been motivated to modify Fujii in the above manner, because said process is known in the art (Col. 6, Lines 16-18 of Ibok).
Claim 7 rejected under 35 U.S.C. 103 as being unpatentable over Fujii, Fischetti and Steiner, in view of Tanaka (U.S. Patent Pub. No. 2009/0294844) of record.
Regarding Claim 7
Fujii as modified by Fischetti and Steiner discloses Claim 1.
Fujii as modified by Fischetti and Steiner is silent with respect to “removing a portion of the amorphous dielectric layer at a bottom of the trench to expose the substrate, wherein the semi-amorphous polysilicon makes an electrical connection to the substrate at the bottom of the trench”.
FIG. 5 of Tanaka discloses a similar method of forming a microelectronic device, comprising removing a portion of the amorphous dielectric layer (401) at a bottom of the trench to expose the substrate (201), wherein the semi-amorphous polysilicon (601, FIG.6) makes an electrical connection to the substrate at the bottom of the trench.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Fujii, as taught by Tanaka. The ordinary artisan would have been motivated to modify Fujii in the above manner for purpose of minimizing memory elements ([0005] of Tanaka).
Claims 8 and 9 rejected under 35 U.S.C. 103 as being unpatentable over Fujii, Fischetti and Steiner, in view of Kim (U.S. Patent Pub. No. 2006/0146640) of record.
Regarding Claim 8
Fujii as modified by Fischetti and Steiner discloses Claim 1.
Fujii as modified by Fischetti and Steiner is silent with respect to “forming a polysilicon outer layer in the trench prior to forming the amorphous dielectric layer, wherein the amorphous dielectric layer is formed on the polysilicon outer layer”.
FIG. 4 of Kim discloses a similar method of forming a microelectronic device, comprising forming a polysilicon outer layer (304) in the trench prior to forming the amorphous dielectric layer (305), wherein the amorphous dielectric layer is formed on the polysilicon outer layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Fujii, as taught by Kim. The ordinary artisan would have been motivated to modify Fujii in the above manner for purpose of satisfying the trend toward high integration in semiconductor devices containing EEPROM cells, particularly flash EEPROM cells ([0010] of Kim).
Regarding Claim 9
Kim discloses forming the amorphous dielectric layer includes thermal oxidation of silicon in the polysilicon outer layer [0047].
Claim 10 rejected under 35 U.S.C. 103 as being unpatentable over Fujii, Fischetti, Steiner and Kim, in view of Seo (U.S. Patent Pub. No. 2012/0007186) of record.
Regarding Claim 10
Fujii as modified by Fischetti, Steiner and Kim discloses Claim 8.
Fujii as modified by Fischetti, Steiner and Kim is silent with respect to “forming a liner in the trench prior to forming the polysilicon outer layer; and removing a portion of the liner at a bottom of the trench to expose the substrate, wherein the polysilicon outer layer makes an electrical connection to the substrate at the bottom of the trench”.
FIG. 2 of Seo discloses a similar method of forming a microelectronic device, comprising forming a liner (126) in the trench (124) prior to forming the polysilicon outer layer (128); and removing a portion of the liner at a bottom of the trench to expose the substrate (100), wherein the polysilicon outer layer makes an electrical connection to the substrate at the bottom of the trench.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Fujii, as taught by Seo. The ordinary artisan would have been motivated to modify Fujii in the above manner for purpose of preventing characteristics from degrading ([0013] of Seo).
Claims 12 and 13 rejected under 35 U.S.C. 103 as being unpatentable over Fujii, Fischetti, Steiner and Kim, in view of Schrems (CN 1213159) of record.
Regarding Claim 12
Fujii as modified by Fischetti, Steiner and Kim discloses Claim 8.
Fujii as modified by Fischetti, Steiner and Kim is silent with respect to “the polysilicon outer layer is doped to have a same conductivity type as the substrate”.
FIG. 1 of Schrems discloses a similar method of forming a microelectronic device, wherein the polysilicon outer layer (161) is doped to have a same (first) conductivity type as the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Fujii, as taught by Schrems. The ordinary artisan would have been motivated to modify Fujii in the above manner for purpose of obtaining a film with low resistance and improving stability of a thinner gate stack (Abstract of Schrems).
Regarding Claim 13
Schrems discloses the liner is formed by a thermal oxidation process.
Claims 14 and 15 rejected under 35 U.S.C. 103 as being unpatentable over Fujii, Fischetti, Steiner and Kim, in view of Wang (U.S. Patent Pub. No. 2017/0287942) of record.
Regarding Claim 14
Fujii as modified by Fischetti, Steiner and Kim discloses Claim 10, wherein the portion of the liner is removed by an etching process.
Fujii as modified by Fischetti, Steiner and Kim is silent with respect to the etching process is “a reactive ion etching process”.
Wang discloses a similar method of forming a microelectronic device, wherein the etching process is a reactive ion etching process [0024].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Fujii, as taught by Wang. The ordinary artisan would have been motivated to modify Fujii in the above manner because such process substitution or replacement would have been considered a mere substitution of art-recognized equivalent values ([0024] of Wang), MPEP 2144.06.
Regarding Claim 15
Wang discloses the portion of the amorphous dielectric layer is removed by a reactive ion etching process.
Claim 26 rejected under 35 U.S.C. 103 as being unpatentable over Fujii, Fischetti and Steiner, in view of Liu (CN 111180451) of record.
Regarding Claim 26
Fujii as modified by Fischetti and Steiner discloses Claim 25.
Fujii as modified by Fischetti and Steiner is silent with respect to “the amorphous dielectric material layer includes a first silicon dioxide layer on the polysilicon gate, a nitrogen-containing dielectric material layer on the first silicon dioxide layer, and a second silicon dioxide layer on the nitrogen-containing dielectric material layer”.
FIG. 5 of Liu discloses a similar method of forming a microelectronic device, wherein the amorphous dielectric material layer includes a first silicon dioxide layer on the polysilicon gate, a nitrogen-containing dielectric material layer on the first silicon dioxide layer, and a second silicon dioxide layer on the nitrogen-containing dielectric material layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Fujii, as taught by Liu. The ordinary artisan would have been motivated to modify Fujii in the above manner for purpose of forming a 3D memory (Abstract of Liu).
Claims 27 and 28 rejected under 35 U.S.C. 103 as being unpatentable over Fujii, Fischetti and Steiner, in view of Jeng (U.S. Patent No. 5,877,074) of record.
Regarding Claim 27
Fujii as modified by Fischetti and Steiner discloses Claim 25.
Fujii as modified by Fischetti and Steiner is silent with respect to “forming a metal-silicide layer on the semi-amorphous polysilicon; and patterning the metal-silicide layer and the semi-amorphous polysilicon to form another gate above the polysilicon gate”.
FIG. 7 of Jeng discloses a similar method of forming a microelectronic device, comprising forming a metal-silicide layer (14) on the semi-amorphous polysilicon; and patterning the metal-silicide layer and the semi-amorphous polysilicon to form another gate above the polysilicon gate.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Fujii, as taught by Jeng. The ordinary artisan would have been motivated to modify Fujii in the above manner for purpose of providing a gate electrode of a semiconductor with improved electrical property (Col. 2, Lines 2-5 of Jeng).
Regarding Claim 28
Modified Fujii discloses the trench extends from the top surface to a metal silicide layer of a transistor of the substrate.
Claim 29 rejected under 35 U.S.C. 103 as being unpatentable over Fujii, Fischetti and Steiner, in view of Qiao (CN 101419981) of record.
Regarding Claim 29
Fujii as modified by Fischetti and Steiner discloses Claim 1.
Fujii as modified by Fischetti and Steiner is silent with respect to “the substrate corresponds to a silicon-on-insulator (SOI) wafer, and wherein the trench extends from the top surface to a buried oxide layer of the SOI wafer”.
FIG. 3 of Qiao discloses a similar method of forming a microelectronic device, the wherein substrate corresponds to a silicon-on-insulator (SOI) wafer, and wherein the trench extends from the top surface to a buried oxide layer (2) of the SOI wafer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Fujii, as taught by Qiao. The ordinary artisan would have been motivated to modify Fujii in the above manner for purpose of reducing the electric field strength of the gate oxide layer (text of Qiao).
Claim 30 rejected under 35 U.S.C. 103 as being unpatentable over Fujii, Fischetti and Steiner, in view of Zhang (CN 1571119) of record.
Regarding Claim 30
Fujii as modified by Fischetti and Steiner discloses Claim 1.
Fujii as modified by Fischetti and Steiner is silent with respect to “the polysilicon core has silicon grains with an average size that is greater than half a minimum lateral dimension of the trench inside the amorphous dielectric material layer”.
However, it is known in the art that higher annealing temperature generally lead to faster grain growth and larger grain sizes, and a more disordered amorphous film may result in larger grain sizes. For example, FIG. 4 of Zhang shows the grain size increases with the thermal energy density applied. Zhang also discloses a sufficient time of grain growth results in large grain size. In particular, annealing amorphous silicon leads to polycrystalline silicon with grain sizes ranging from a few nanometers to micrometers.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the method of Fujii with sufficiently high thermal energy density for conversion and/or sufficiently long grain growth time, as taught by Zhang, a polysilicon core having silicon grains with an average size that is greater than half a minimum lateral dimension of the trench inside the dielectric material layer can be obtained. The ordinary artisan would have been motivated to modify Fujii in the above manner to meet their design needs such as conductance, etching rates, etc.
Pertinent Art
Ku (U.S. Patent Pub. No. 2005/0153530) discloses a mixture of polysilicon and amorphous silicon as trench filling material. Kakimoto (U.S. Patent Pub. No. 2013/0005142) discloses forming a seed layer (58) in the trench, the seed layer including a dielectric material [0079]. Hideo (U.S. Patent Pub. No. 2004/0259326) discloses the semi-amorphous polysilicon has amorphous silicon regions, separated by polycrystalline silicon. US. 20200098986.
Response to Arguments
Applicant’s arguments with respect to Claim 1 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
Prosecution Insights