DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 2, claims 1-9, 11-14, 16-18, 20-23 corresponding to Fig. 8, in the reply filed on 11/03/2025 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. 20220173191.
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Regarding claim 1, fig. 3 of Kim discloses a display device comprising:
a base layer SUB;
a first conductive layer 110 disposed on the base layer;
an gate insulating layer GI1 disposed on the first conductive layer;
a first semiconductor layer 210 disposed on the gate insulating layer GI1 and including a silicon semiconductor;
a first insulation layer GI2 disposed on the first semiconductor layer; and
a second semiconductor layer 410 including an oxide semiconductor (par [0153]) and disposed on the first insulation layer, wherein:
the first conductive layer 110 is a first electrode of a first capacitor CST_1;
the first semiconductor layer 210 is a second electrode of the first capacitor and a first electrode of a second capacitor (note that 210 and 410 is inherently a capacitor); and
the second semiconductor layer 410 is a second electrode of the second capacitor.
Kim does not disclose that the gate insulating layer GI1 is an inorganic layer.
However, par [0101] of Kim discloses that a third gate insulating layer GI3 may include silicon oxide, silicon nitride, titanium oxide, tantalum oxide, or the like.
As such it would have been obvious to form a device comprising wherein the gate insulating layer GI1 is an inorganic layer in order to use a desired material with a desired dielectric constant for a desired capacitance.
Kim does not disclose that the first semiconductor layer is one including an oxide semiconductor.
However, par [0153] of Kim discloses that a second active pattern 410′ may include an oxide semiconductor. Note that semiconductor can be silicon semiconductor or oxide semiconductor depending on the resistance and speed requirement.
As such it would have obvious to form a device comprising wherein the first semiconductor layer is one including an oxide semiconductor instead of silicon semiconductor in order to obtain a desire resistance.
Regarding claims 2 and 11, fig. 3 of Kim discloses wherein: the first conductive layer comprises a (1-1)th conductive pattern layer 210 and a (1-2)th conductive pattern layer 220 which are spaced apart from each other in a plan view (this is necessary the case); the first semiconductor layer comprises a (1-1)th semiconductor pattern layer 210 and a (1-2)th semiconductor pattern layer 220 which are spaced apart from each other in a plan view; the second semiconductor layer comprises a (2-1)th semiconductor pattern layer 420 and a (2-2)th semiconductor pattern layer 410 which are spaced apart from each other in a plan view; each of the (1-1)th semiconductor pattern layer 110, the (1-2)th semiconductor pattern layer 210, and the (2-2)th semiconductor pattern layer 410 overlaps the (1-1)th conductive pattern layer 210 in a plan view (this necessary the case); and the (2-1)th semiconductor pattern layer 420 overlaps the (1-2)th conductive pattern layer 220 in a plan view (this necessary the case).
Allowable Subject Matter
Claims 16-18, 20-23 allowed.
Claims 16 and 20 recites "a first capacitor electrically connected between a first node and a second node; and a second capacitor electrically connected between the second voltage line and the second node ", this feature in combination with the other features of the claim, is not taught by the references of record.
Claims 3-9 and 12-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
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