DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/27/2026 has been entered.
Response to Amendments
Applicant's response of 04/08/2026 has been acknowledged. Claims 1-2
and 11 have been amended. No new matter has been added.
This office action considers claims 1-20 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant's arguments of 04/08/2026 with respect to the rejections of claims have
been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1, 3-5, 7, 10, 11, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20210233991 A1 – hereinafter Lee) in view of Dong (US 20210327344 A1 – hereinafter Dong) and Park et al. (US 20120293496 A1 – hereinafter Park).
Regarding independent claim 1, Lee teaches
(Currently Amended) A display panel (10 – Fig. 4 – [0057] – “display
panel 10”) comprising:
a driving voltage line (PL – Fig. 5 – [0081] – “driving voltage line PL”)
configured to provide a driving voltage (ELVDD – [0088] – “driving voltage line PL transfers the driving voltage ELVDD”), the driving voltage line (PL) being in a display area (DA – Fig. 4 – [0077] – “display area DA” – Fig. 4 shows this);
an organic light-emitting diode (OLED – Fig. 5 – [0094] – “pixel electrode of
the OLED”);
a driving transistor (T1 – Fig. 5 – [0087] – “driving thin film transistor T1”)
electrically connected between the driving voltage line (PL) that is configured to provide the driving voltage (ELVDD) and the organic light-emitting diode driving transistor (OLED);
a data write transistor (T2 – [0087] – “switching thin film transistor T2”) electrically connected between the driving transistor (DL – Fig. 5 – [0088] – “data line DL”);
a first voltage line configured to provide a first voltage, the first voltage line extending in a first direction in a display area;
a first transistor electrically connected to a first terminal of
a first vertical voltage line extending in a second direction perpendicular to the first direction in a display area and electrically connected to the first voltage line that is configured to provide the first voltage; and
a second transistor (T5 – Fig. 5 – [0087] – “operation control thin film transistor T5”) electrically connected to the first terminal of (T1 – [0089] – “the driving thin film transistor T1 is connected to the driving voltage line PL through the operation control thin film transistor T5”) and the driving voltage line (PL) that is configured to provide the driving voltage (ELVDD – [0088] – “driving voltage line PL transfers the driving voltage ELVDD”).
Lee does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Dong teaches
a first transistor (T8 – Fig. 8A – [0057] – “second bias transistor T8 is electrically connected to the first electrode of the drive transistor T1”) electrically connected to a first terminal of (T1 – Fig. 8A – [0057] – “the drive transistor T1”) and the first voltage line (V1 – Fig. 8A – [0074] – “first power voltage terminal V1” – this is interpreted as a voltage line).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first transistor structure as taught by Dong into Lee.
An ordinary artisan would have been motivated to use the known technique of Dong in the manner set forth above to produce the predictable result [0003] – “Organic light emitting diode (OLED) display devices have advantages of self-luminescence, high contrast, low energy consumption, wide viewing angle, fast response, being capable to be used in a flexible panel, wide using temperature range, simple manufacture and so on, and have broad development prospects.”
Lee and Dong do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Park teaches
a first voltage line (HE1-ELVDD – Fig. 13 – [0235] – “first horizontal power line HE1-ELVDD for transmitting the voltage to the first unit area pixel E in the horizontal direction”) configured to provide a first voltage ([0070] – “The first power voltage may be supplied as a first level voltage for a first period during which the first group pixels concurrently emit light, and the second power voltage is supplied as a second level voltage for a second period during which the second group pixels concurrently emit light” – hereinafter ‘FV’), the first voltage line ([0205] – “first power voltage EVDD transmitted from the first power line ELVDD through the contact hole 1151” – ELVDD power line provide different voltages) extending in a first direction (Fig. 13 annotated, see below – [0235] – “the horizontal direction” – hereinafter ‘x’) in a display area ([0114] – “FIG. 2 shows a display panel where the plurality of first unit area pixels E and the plurality of second unit area pixels O are alternately arranged according to a 1.times.1 dot weave array” – as E and O are in the display area, Fig. 13 shows this, hereinafter ‘DA’),
a first vertical voltage line (VE1-ELVDD – Fig. 13 – [0233] – “the first vertical power line VE1-ELVDD”) extending in a second direction (Fig. 13 annotated, see below – [0232] – “first vertical power lines V-ELVDD extended in the vertical direction” – hereinafter ‘y’) perpendicular to the first direction (x) in a display area (DA – Fig. 13 shows this) and electrically connected to the first voltage line (HE1-ELVDD – [0237] – “first power voltage EVDD from the first vertical power line VE1-ELVDD, and the pixel transmits the first power voltage EVDD to sub-pixels of the pixel through the first horizontal power line HE1-ELVDD” – Fig. 13 shows this) that is configured to provide the first voltage (FV).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first voltage line structure as taught by Park into Lee and Dong.
An ordinary artisan would have been motivated to use the known technique of Park in the manner set forth above to produce the predictable result of [0023] – “The respective first group pixels and the respective second group pixels include at least one power connection wire coupled to the first electrodes of the storage capacitors and configured to respectively transmit the first power voltage and the second power voltage supplied to the first electrodes of the storage capacitors.”
Regarding claim 2, Lee, as modified by Dong and Park, teaches claim 1 from which claim 2 depends. Lee further teaches
(Currently Amended) The display panel of claim 1, wherein
the data write transistor (T2 – Fig. 5 – [0090] – “transistor T2 is connected to the data line DL, and a switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1”) is electrically connected to the first terminal of the driving transistor (T1 – Fig. 5 – [0090] – “transistor T2 is connected to the data line DL, and a switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1”) (DL – Fig. 5 – [0090] – “transistor T2 is connected to the data line DL, and a switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1”).
Regarding claim 3, Lee, as modified by Dong and Park, teaches claim 1 from which claim 3 depends. Lee further teaches
(Original) The display panel of claim 1, further comprising:
a second voltage line extending in the first direction;
a third transistor electrically (T6 – Fig. 5 – [0094] – “transistor T6”) connected
between the organic light-emitting diode (OLED) and the second voltage line (170 – Fig. 4 – [0081] – “first and second powers ELVDD and ELVSS to the first and second power supply lines 160 and 170 through first and second connection wirings 161 and 171”); and
a second vertical voltage line extending in the second direction and electrically connected to the second voltage line.
Lee and Dong do not expressly disclose the other limitations of claim 3.
However, in an analogous art, Park teaches
a second voltage line (HO2-ELVDD – Fig. 13 – [0258] – “horizontal power line
HO2-ELVDD connected to the pixels O32 and O21”) extending in the first direction (x);
a second vertical voltage line (VO1-ELVDD – Fig. 13 – [0258] – “power line VO1-ELVDD”) extending in the second direction (y) and electrically connected to the second voltage line (HO2-ELVDD – [0258] – “the first power line VO1-ELVDD using the above-stated method, the first power voltage is transmitted in the horizontal direction through the first horizontal power line HO2-ELVDD”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second voltage line structure as taught by Park into Lee and Dong.
An ordinary artisan would have been motivated to use the known technique of Park in the manner set forth above to produce the predictable result of as stated above in claim 1.
Regarding claim 4, Lee, as modified by Dong and Park, teaches claim 3 from which claim 4 depends. Lee further teaches
(Previously Presented) The display panel of claim 3, further
comprising:
a gate line (SL-1 – Fig. 5 – [0088] – “the previous scan line SL−1” – this is
interpreted as a gate line) configured to apply a control signal (Sn-1 – [0088] – “the previous scan line SL−1 configured to transfer a previous scan signal Sn−1”) to a gate of the first transistor (T1) and a gate ([0088] – “the scan line SL” – this is a gate one providing the signal Sn and corresponds to what is shown in applicant’ Figs. 2A and 2B) of the third transistor (T3 – Fig. 5 – [0087] – “compensation thin film transistor T3”), the gate line (SL-1 – [0114] – “scan line SL−1 may extend in the x-direction”) extending in the first direction (x).
Regarding claim 5, Lee, as modified by Dong and Park, teaches claim 1 from which claim 5 depends. Lee further teaches
(Original) The display panel of claim 1, further comprising:
a third voltage line (VL – Fig. 5 – [0088] – “initialization voltage line VL transfers
an initialization voltage Vint”) extending in the first direction (x);
a fourth transistor electrically (T4 – Fig. 5 – [0088] – “first initialization thin film
transistor T4”) connected between a gate of the driving transistor (T1) and the third voltage line (VL); and
a third vertical voltage line extending in the second direction and electrically connected to the third voltage line.
Lee and Dong do not expressly disclose the other limitations of claim 5.
However, in an analogous art, Park teaches
a third vertical voltage line (VE2-ELVDD – Fig. 13 – [0315] – “vertical power line VE2-ELVDD”) extending in the second direction (y) and electrically connected to the third voltage line (HE1-ELVDD – Fig. 13 – [0315] – “power line HE1-ELVDD is connected with the first vertical power line VE1-ELVDD passing the pixel E11 and the first vertical power line VE2-ELVDD”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the third vertical voltage line structure as taught by Park into Lee and Dong.
An ordinary artisan would have been motivated to use the known technique of Park in the manner set forth above to produce the predictable result of as stated above in claim 1.
Regarding claim 7, Lee, as modified by Dong and Park, teaches claim 1 from which claim 7 depends. Lee further teaches
(Original) The display panel of claim 1, further comprising:
a fifth transistor (T3 – Fig. 5 – [0087] – “compensation thin film transistor T3”)
electrically connected between a gate of the driving transistor (T1) and a second node (Fig. 5 annotated, see below – hereinafter N3), the second node (N3) being between the driving transistor (T1) and the organic light-emitting diode (OLED).
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Regarding claim 10, Lee, as modified by Dong and Park, teaches claim 1 from which claim 10 depends. Lee further teaches
(Original) The display panel of claim 1, wherein the driving voltage
line (PL) comprises:
a first driving voltage line (163) extending in the first direction (x); and
a second driving voltage line (HL – Fig. 7 – [0118] – “electrode voltage line HL
may extend in the x-direction”) extending in the second direction (y) and electrically connected to the first driving voltage line (163).
Regarding independent claim 11, Lee teaches
(Currently Amended) A display panel comprising:
a substrate (100 – Fig. 4 – [0058] – “substrate 100”) comprising a display area
(DA – Fig. 4 – [0055] – “display area DA”) and a peripheral area (NDA2 – Fig. 4 – [0052] – “second non-display area NDA2 surrounding an outer periphery of the display area DA”) surrounding the display area (DA);
a plurality of pixel circuits in the display area;
a plurality of first voltage lines configured to provide a first voltage, the plurality of first voltage lines extending in a row direction in the display area; and
a plurality of first vertical voltage lines extending in a column direction in the display area, at intervals of a first number of columns, and electrically connected to the plurality of first voltage lines that are configured to provide the first voltage, wherein
each pixel circuit ([claim 6] – “plurality of pixel circuits” – hereinafter ‘PXC’) of the plurality of pixel circuits (PXC) comprises,
a driving transistor (T1 – Fig. 5 – [0090] – “transistor T2 is connected to the data line DL, and a switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1”);
a data write transistor (T2 – Fig. 5 – [0090] – “transistor T2 is connected to the data line DL, and a switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1”) electrically connected to a first terminal of (T1) and a data line (DL – Fig. 5 – [0090] – “transistor T2 is connected to the data line DL, and a switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1”);
a first transistor electrically connected to the first terminal of configured to provide the first voltage, wherein, the first voltage line is [[being]] in a corresponding row from among the plurality of first voltage lines; and
a second transistor (T5 – Fig. 5 – [0087] – “operation control thin film transistor T5”) electrically connected to the first terminal of (T1 – [0089] – “the driving thin film transistor T1 is connected to the driving voltage line PL through the operation control thin film transistor T5”) and the driving voltage line (PL) that is configured to provide the driving voltage (ELVDD – [0088] – “driving voltage line PL transfers the driving voltage ELVDD”) .
Lee does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Dong teaches
a first transistor (T8 – Fig. 8A – [0057] – “second bias transistor T8 is
electrically connected to the first electrode of the drive transistor T1”) electrically connected to the first terminal of (T1 – Fig. 8A – [0057] – “the drive transistor T1”) and a first voltage line (V1 – Fig. 8A – [0074] – “first power voltage terminal V1” – this is interpreted as a voltage line) configured to provide the first voltage, wherein (V.sub.dd – Fig. 2 – [0122] – “the first power voltage signal V.sub.dd output by the first power voltage terminal V1”), the first voltage line (V1) is [[being]] in a corresponding row from among the plurality of first voltage lines (V1).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first transistor structure as taught by Dong into Lee.
An ordinary artisan would have been motivated to use the known technique of Dong in the manner set forth above to produce the predictable result [0003] – “Organic light emitting diode (OLED) display devices have advantages of self-luminescence, high contrast, low energy consumption, wide viewing angle, fast response, being capable to be used in a flexible panel, wide using temperature range, simple manufacture and so on, and have broad development prospects.”
Lee and Dong do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Park teaches
a plurality of pixel circuits ([0034] – “Each of the first group pixels and each of the second group pixels respectively may include at least one sub-pixel including an emission unit comprising an organic light emitting diode and a circuit unit for supplying a driving current according to an image data signal to the emission unit” – this describes a plurality of pixel circuits, hereinafter ‘PC’) in the display area ([0114] – “FIG. 2 shows a display panel where the plurality of first unit area pixels E and the plurality of second unit area pixels O are alternately arranged according to a 1.times.1 dot weave array” – as E and O are in the display area, Fig. 13 shows this, hereinafter ‘DA’);
a plurality of first voltage lines (HE#-ELVDD – Fig. 13 – [0234] – “first horizontal power line HE-ELVDD for horizontally transmitting the first power voltage EVDD to the first unit area pixel E, and a first horizontal power line HO-ELVDD for horizontally transmitting the third power voltage OVDD to the second unit area pixel O, are alternately arranged in each pixel row” – # represents numbers 1, 2, 3, and so on) configured to provide a first voltage ([0070] – “The first power voltage may be supplied as a first level voltage for a first period during which the first group pixels concurrently emit light, and the second power voltage is supplied as a second level voltage for a second period during which the second group pixels concurrently emit light” – hereinafter ‘FV’), the plurality of first voltage lines (HE#-ELVDD – [0205] – “first power voltage EVDD transmitted from the first power line ELVDD through the contact hole 1151” – ELVDD power line provide different voltages) extending in a row direction (Fig. 13 annotated, see below – [0235] – “the horizontal direction” – hereinafter ‘x’) in the display area (DA); and
a plurality of first vertical voltage lines (VE#-ELVDD – Fig. 13 – [0232] – “first power line VE-ELVDD for supplying the first power voltage EVDD to a first unit area pixel E, and a first power line VO-ELVDD for supplying a third power voltage OVDD to a second unit area pixel O, are alternately provided the respective pixel lines” – # represents numbers 1, 2, 3, and so on) extending in a column direction (Fig. 13 annotated, see below – [0232] – “first vertical power lines V-ELVDD extended in the vertical direction” – hereinafter ‘y’) in the display area (DA), at intervals of a first number of columns (Fig. 13 shows this), and electrically connected to the plurality of first voltage lines (HO2-ELVDD – [0258] – “the first power line VO1-ELVDD using the above-stated method, the first power voltage is transmitted in the horizontal direction through the first horizontal power line HO2-ELVDD”) that are configured to provide the first voltage (FV).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first voltage line structure as taught by Park into Lee and Dong.
An ordinary artisan would have been motivated to use the known technique of Park in the manner set forth above to produce the predictable result of as stated above in claim 1.
Regarding claim 16, Lee, as modified by Dong and Park, teaches claim 11 from which claim 16 depends. Lee further teaches
(Previously Presented) The display panel of claim 11, further
comprising:
a plurality of third voltage lines (VL – Fig. 5 – [0088] – “initialization voltage
line VL transfers an initialization voltage Vint”) extending in the row direction (x) in the display area (DA); and
a plurality of third vertical voltage lines extending in the column direction in the display area, at the intervals of the first number of columns, and electrically connected to the plurality of third voltage lines,
wherein each pixel circuit (PXC) of the plurality of pixel circuits (PXC) further comprises a fourth transistor (T4) electrically connected between a gate of the driving transistor (T1) and a third voltage line (VL) (VL).
Lee and Dong do not expressly disclose the other limitations of claim 16.
However, in an analogous art, Park teaches
a plurality of third vertical voltage lines (VE2-ELVDD – Fig. 13 – [0315] – “vertical power line VE2-ELVDD”) extending in the column direction (y) in the display area (DA), at the intervals of the first number of columns, and electrically connected to the plurality of third voltage lines (HE1-ELVDD – Fig. 13 – [0315] – “power line HE1-ELVDD is connected with the first vertical power line VE1-ELVDD passing the pixel E11 and the first vertical power line VE2-ELVDD”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the third voltage line structure as taught by Park into Lee and Dong.
An ordinary artisan would have been motivated to use the known technique of Park in the manner set forth above to produce the predictable result of as stated above in claim 1.
Claims 6, 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Dong, Park, and Lai et al. (US 20220051625 A1 – hereinafter Lai).
Regarding claim 6, Lee, as modified by Dong and Park, teaches claim 5 from which claim 6 depends. Lee further teaches
(Previously Presented) The display panel of claim 5, wherein
the fourth transistor (T4) comprises a pair of sub-transistors (Fig. 5 annotated, see below – hereinafter ‘T4-1’ and T4-2’) electrically connected in series, and the display panel further (10) comprises,
a capacitor (Cst – Fig. 5 – [0085] – “storage capacitor Cst”) electrically connected between the driving voltage line (PL) and a node between the pair of sub-transistors.
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Lee, Dong, and Park do not expressly disclose the limitations of claim 6.
However, in an analogous art, Lai teaches
a node (N2 Fig. 2 – [0020] – “a connection node between a first sub-transistor (T11) and a second sub-transistor (T12) in the first double-gate transistor (T1) is a second node (N2)”) between the pair of sub-transistors (T11 and T12 – Fig. 2 – [0020] – “a connection node between a first sub-transistor (T11) and a second sub-transistor (T12) in the first double-gate transistor (T1) is a second node (N2)”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the sub-transistor connection structure as taught by Lai into Lee, Dong, and Park.
An ordinary artisan would have been motivated to use the known technique of Lai in the manner set forth above to produce the predictable result [0005] – “to stabilize a potential of a gate of a drive transistor in a pixel circuit, maintain the stability of the brightness of a light-emitting element, and improve the display effect of the display panel.”
Regarding claim 8, Lee, as modified by Dong and Park, teaches claim 7 from which claim 8 depends. Lee further teaches
(Previously Presented) The display panel of claim 7, wherein
the fifth transistor (T3) comprises a pair of sub-transistors (Fig. 5 annotated,
see above – hereinafter ‘T3-1’ and T3-2’) electrically connected in series, and
the display panel (10) further comprises,
a capacitor electrically connected between the driving voltage line and a
node between the pair of sub-transistors.
Lee, Dong, and Park do not expressly disclose the limitations of claim 8.
However, in an analogous art, Lai teaches
a capacitor (C3 – Fig. 2 – [0026] – “third capacitor (C3) is connected to
the third node (N3)”) electrically connected between the driving voltage line (S2 – Fig. 2 – {[0020] – “A potential of the third node (N3) is raised due to the third capacitor (C3) and a second scan signal (S2) (high level signal)”}, {[0035] – “power supply voltage signal (PVDD) is a constant high level signal”} – this is interpreted that S2 is connected to the voltage lien PL since it is also a high level signal) and a node (N3 – Fig. 2 – [0024] – “second double-gate transistor (T2) includes a third sub-transistor (T23) and a fourth sub-transistor (T24), and a connection node between the third sub-transistor (T23) and the fourth sub-transistor (T24) is a third node (N3)”) between the pair of sub-transistors (N3 – Fig. 2 – [0024] – “second double-gate transistor (T2) includes a third sub-transistor (T23) and a fourth sub-transistor (T24), and a connection node between the third sub-transistor (T23) and the fourth sub-transistor (T24) is a third node (N3)”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the sub-transistor connection structure as taught by Lai into Lee, Dong, and Park.
An ordinary artisan would have been motivated to use the known technique of Lai in the manner set forth above to produce the predictable result as stated above in claim 6.
Regarding claim 9, Lee, as modified by Dong and Park, teaches claim 1 from which claim 9 depends. Lee further teaches
(Original) The display panel of claim 1, further comprising:
a fourth transistor (T4) electrically connected between a gate of the driving
transistor (T1) and a third voltage line (VL) and comprising a pair of sub-transistors (T4-1 and T4-2) electrically connected in series;
a fifth transistor (T3) electrically connected between the gate of the driving transistor (T1) and a node (N3), the node (N3) being between the driving transistor (T1) and the organic light-emitting diode (OLED), the fifth transistor (T3) comprising a pair of sub-transistors (T3-1 and T3-2) electrically connected in series;
a first capacitor (Cst – Fig. 5. – [0085] – “storage capacitor Cst”) electrically connected between the driving voltage line (PL) and the gate of the driving transistor (T1);
a second capacitor electrically connected between the driving voltage line and a node between the pair of sub-transistors of the fourth transistor; and
a third capacitor electrically connected between the driving voltage line and a node between the pair of sub-transistors of the fifth transistor.
Lee, Dong, and Park do not expressly disclose the limitations of claim 9.
However, in an analogous art, Lai teaches
a second capacitor (C3) electrically connected between the driving voltage line (S2) and a node (N3) between the pair of sub-transistors (T23 and T24) of the fourth transistor (T2 – Fig. 2 – [0024] – “second double-gate transistor (T2)”); and
a third capacitor (C2 – Fig. 2 – [0020] – “the second node (N2) is raised by a second capacitor (C2) due to this high level signal”) electrically connected between the driving voltage line (S1 – Fig. 2 – {[0020] – “a first scan signal (S1) (high level signal)”}, {[0035] – “power supply voltage signal (PVDD) is a constant high level signal”} – this is interpreted that S1 is connected to the voltage lien PL since it is also a high level signal) and a node (N2 – Fig., 5 – [0020] – “second node (N2)”) between the pair of sub-transistors (T11 and T12) of the fifth transistor (T1 – Fig. 5 – [0020] – “double-gate transistor (T1)”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the sub-transistor and capacitor structure as taught by Lai into Lee, Dong, and Park.
An ordinary artisan would have been motivated to use the known technique of Lai in the manner set forth above to produce the predictable result as stated above in claim 6.
Claims 12-14, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Dong, Park, and Hayashi (US 20060202611 A1 – hereinafter Hayashi).
Regarding claim 12, Lee, as modified by Dong and Park, teaches claim 11 from which claim 12 depends. Lee further teaches
the peripheral area (NDA2).
Lee, Dong, and Park do not expressly disclose the other limitations of claim 12.
However, in an analogous art, Hayashi teaches
(Previously Presented) The display panel of claim 11, further comprising:
a first voltage supply line (Lr2) in the peripheral area,
wherein the plurality of first voltage lines (Lr1) and the plurality of first
vertical voltage lines (Lr2) are electrically connected to the first voltage supply line (LR) in the peripheral area.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the voltage lines structure as taught by Hayashi into Lee, Dong, and Park.
An ordinary artisan would have been motivated to use the known technique of Hayashi in the manner set forth above to produce the predictable result to [0009] – “provides an organic EL device capable of preventing a short circuit from consecutively occurring, and a reliable electronic apparatus.”
Regarding claim 13, Lee, as modified by Dong and Park, teaches claim 11 from which claim 13 depends. Lee further teaches
(Previously Presented) The display panel of claim 11, further
comprising:
a plurality of second voltage lines extending in the row direction in the display
area; and
a plurality of second vertical voltage lines extending in the column direction in the display area, at intervals of a second number of columns, and electrically connected to the plurality of second voltage lines, wherein
each pixel circuit (PXC) of the plurality of pixel circuits (PXC) further comprises,
a third transistor (T6 – Fig. 5 – [0087] – “emission control thin film transistor T6”) connected between a display element (OLED) and a second voltage line (163), the second voltage line (163) being in a corresponding row (x) from among the plurality of second voltage lines (160).
Lee, Dong, and Park do not expressly disclose the other limitations of claim 13.
However, in an analogous art, Hayashi teaches
a plurality of second voltage lines (Lg1– Fig. 3 – [0050] – “first sub-power lines
Lr1, Lg1, and Lb1 are provided so as to be parallel in a row direction”) extending in the row direction ([0050] – “first sub-power lines Lr1, Lg1, and Lb1 are provided so as to be parallel in a row direction” – hereinafter ‘x’) in the display area (DA); and
a plurality of second vertical voltage lines (Lg2 – Fig. 3 – [0050] – “second sub-power lines Lr2, Lg2, and Lb2 are provided so as to be parallel in a column direction”) extending in the column direction ([0050] – “second sub-power lines Lr2, Lg2, and Lb2 are provided so as to be parallel in a column direction” – hereinafter ’y’) in the display area (DA), at intervals of a second number of columns, and electrically connected to the plurality of second voltage lines (Lg1 – Fig. 3 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the voltage lines structure as taught by Hayashi into Lee, Dong, and Park.
An ordinary artisan would have been motivated to use the known technique of Hayashi in the manner set forth above to produce the predictable result as stated above in claim 12.
Regarding claim 14, Lee, as modified by Dong, Park, and Hayashi, teaches claim 13 from which claim 14 depends. Lee further teaches
(Previously Presented) The display panel of claim 13, further
comprising:
a second voltage supply line (163) in the peripheral area (NDA2),
wherein the plurality of second vertical voltage lines (PL) in the display area (DA – Fig. 4 – [0077] – “display area DA” – Fig. 4 shows this) are electrically connected to the second voltage supply line (163) in the peripheral area (NDA2 – Fi.g 4 shows this).
Regarding claim 17, Lee, as modified by Dong and Park, teaches claim 16 from which claim 17 depends. Lee further teaches
the peripheral area (NDA2).
Lee, Dong, and Park do not expressly disclose the other limitations of claim 17.
However, in an analogous art, Hayashi teaches
(Previously Presented) The display panel of claim 16, further comprising:
a third voltage supply line (LB – Fig. 3 – [0049] – “power lines include main
power lines LR, LG, and LB”) in the peripheral area,
wherein the plurality of third vertical voltage lines (Lb2) in the display area
(DA) are electrically connected to the third voltage supply line (Lb2 – Fig. 3 – [0050] – “second sub-power lines Lr2, Lg2, and Lb2 are provided so as to be parallel in a column direction”) in the peripheral area.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the third voltage lines structure as taught by Hayashi into Lee, Dong, and Park.
An ordinary artisan would have been motivated to use the known technique of Hayashi in the manner set forth above to produce the predictable result as stated above in claim 12.
Regarding claim 18, Lee, as modified by Dong and Park, teaches claim 16 from which claim 18 depends. Lee, Dong, and Park do not expressly disclose the limitations of claim 18.
However, in an analogous art, Hayashi teaches
(Previously Presented) The display panel of claim 16, wherein
one of the plurality of first vertical voltage lines (Lr2) is between a first pair
of adjacent pixel areas (26 – Fig. – [0065] – “the pixel area 26 of the organic EL device”), and
one of the plurality of third vertical voltage lines (Lg2) is between a second pair of adjacent pixel areas (26).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the third voltage lines structure as taught by Hayashi into Lee, Dong, and Park.
An ordinary artisan would have been motivated to use the known technique of Hayashi in the manner set forth above to produce the predictable result as stated above in claim 12.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Dong, Park, Hayashi, and Yang et al. (US 20230028746 A1 – hereinafter Yang-746).
Regarding claim 15, Lee, as modified by Dong, Park, and Hayashi, teaches claim 13 from which claim 15 depends. Lee, Dong, Park, and Hayashi do not expressly disclose the limitations of claim 15.
However, in an analogous art, Yang-746 teaches
(Previously Presented) The display panel of claim 13, wherein
the first number of columns is greater than the second number (the number
of first vertical voltage lines is greater than the number of second vertical voltage lines as defined below) of columns,
one of the plurality of first vertical voltage lines (005a and 006a – Fig. 1A –
[0035] – {“first voltage line 005 includes a first portion 005a and a second portion 005b. The first portion 005a extends in a column direction”}, {“Similarly, the second voltage line 006 includes a first portion 006a and a second portion 006b. The first portion 006a extends in the column direction”}) is between a first pair of adjacent pixel areas (002 – Fig. 1A – [0033] – “light-emitting unit 002 includes a driving circuit and a plurality of light-emitting elements” – this is a pixel area), and
one of the plurality of second vertical voltage lines (0061 – Fig. 1B – [0039] – “additional voltage lines 0061”) is between a second pair of adjacent pixel areas (002).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the voltage lines column structure as taught by Yang-746 into Lee, Dong, Park, and Hayashi.
An ordinary artisan would have been motivated to use the known technique of Yang-746 in the manner set forth above to produce the predictable result [0033] – “each light-emitting unit 002 includes a driving circuit and a plurality of light-emitting elements.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Dong, Park, Lai, and Yang et al. (CN 112289267 A – hereinafter Yang).
Regarding claim 19, Lee, as modified by Dong and Park, teaches claim 16 from which claim 19 depends. Lee further teaches
(Previously Presented) The display panel of claim 16, wherein each
pixel circuit (PXC) of the plurality of pixel circuits (PXC) comprises:
a fifth transistor (T3 – Fig. 5 – [0087] – “compensation thin film transistor T3”)
electrically connected between the gate of the driving transistor (T1) and a second node (Fig. 5 annotated, see below – hereinafter N3), the second node (N3) being between the driving transistor (T1) and an organic light-emitting diode (OLED);
a first capacitor (CST – Fig. 5 – [0089] – “storage capacitor Cst”) comprising a first electrode (Cst1 – Fig. 5 – [0089] – “first storage capacitor plate Cst1”) including the gate of the driving transistor (T1) and a second electrode (Cst2 – Fig. 5 – [0098] – “second storage capacitor plate Cst2 of the storage capacitor Cst”) above the first electrode (Cst1 – Fig. 5 shows this).
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Lee, Dong, and Park do not expressly disclose the limitations of claim 19.
However, in an analogous art, Lai teaches
a second capacitor (C3 – Fig. 1 – [0026] – “third capacitor (C3)”) comprising a third electrode ([0026] – “a second pole plate of the third capacitor (C3) is connected to the third node (N3)” – node N3 is connected to T2, hereinafter ‘3E’) and a fourth electrode ([0026] – “first pole plate of the third capacitor” – hereinafter ‘4E’) above the third electrode (3E);
a third capacitor (C2 – Fig. 1 – [0026] – “second capacitor (C2)”) comprising a fifth electrode ([0026] – “a second pole plate of the second capacitor (C2) is connected to the second node (N2)” – node N2 is connected to T1, hereinafter ‘5E’) and a sixth electrode ([0026] – “first pole plate of the second capacitor” – hereinafter ‘6E’) above the fifth electrode (5E),
wherein the fifth transistor (T2 – Fig. 1 – [0019] – “double-gate transistor (T2)”) comprises a first semiconductor layer (T2 – Fig. 1 – [0026] – “the second double-gate transistor (T2)” – each transistor has a semiconductor layer) and the fourth transistor comprises a second semiconduction layer (T1 – Fig. 1 – [0033] – “the first double-gate transistor (T1)” – each transistor has a semiconductor layer), and
wherein the third electrode of the second capacitor (C3) is electrically connected to the first semiconductor layer, and the fifth electrode of the third capacitor (C2) is electrically connected to the second semiconductor layer.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the capacitor structure as taught by Lai into Lee, Dong, and Park.
An ordinary artisan would have been motivated to use the known technique of Lai in the manner set forth above to produce the predictable result as stated above in claim 6.
Lee, Dong, Park, and Lai do not expressly disclose the limitations of claim 19.
However, in an analogous art, Yang teaches
wherein the third electrode of the second capacitor is electrically connected to the first semiconductor layer ([0043] – “The initialization signal line Ref at the overlap position with the active layer of the first sub-transistor T11 and the second sub-transistor T12 in series serves as one plate of the first coupling capacitor C1, and the active layer of the first sub-transistor T11 and the second sub-transistor T12 in series serves as the other plate of the first coupling capacitor C1”), and the fifth electrode of the third capacitor is electrically connected to the second semiconductor layer ([0043] teaches this connection).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the electrical connection structure as taught by Yang into Lee, Dong, Park, and Lai.
An ordinary artisan would have been motivated to use the known technique of Yang in the manner set forth above to produce the predictable result of [0033] – “In order to make the light-emitting element emit light, a first voltage signal needs to be provided to a first voltage terminal 003 of each light-emitting unit 002, and a second voltage signal needs to be provided to a second voltage terminal 004 of each light-emitting unit 002.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Dong, Park, Lai, Yang, and Dokania et al. (US 20230284456 A1 – hereinafter Dokania).
Regarding claim 20, Lee, as modified by Dong, Park, Lai, and Yang teaches claim 19 from which claim 19 depends. Lee further teaches
the second electrode (Cst2) of the first capacitor (Cst).
Lee, Dong, Park, and Yang do not expressly disclose the limitations of claim 20.
However, in an analogous art, Lai teaches
(Previously Presented) The display panel of claim 19, wherein
the third electrode (3E) of the second capacitor (C1) and the fifth electrode
(5E) of the third capacitor (C2) each include a semiconductor material, and
the second electrode of the first capacitor, the fourth electrode (4E), of the second capacitor (C1) and the sixth electrode (6E) of the third capacitor (C2) are integral with each other and are electrically connected to the driving voltage line (PVDD).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the capacitor structure as taught by Lai into Lee, Dong, and Park.
An ordinary artisan would have been motivated to use the known technique of Lai in the manner set forth above to produce the predictable result as stated above in claim 6.
Lee, Dong, Park, Yang, and Lai do not expressly disclose the limitations of claim 20.
However, in an analogous art, Dokania teaches
are integral with each other ({[0687] – “the metal plane is coupled to individual bottom electrodes of the first capacitor, the second capacitor, the third capacitor”}, {[0310] – “capacitors on shared electrode 1301 or metal plane 1401”} the capacitors share an electrode therefore are integral to each other).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the capacitor structure as taught by Dokania into Lee, Dong, Park, Yang, and Lai.
An ordinary artisan would have been motivated to use the known technique of Dokania in the manner set forth above to produce the predictable result of [0091] – “a configuration for efficiently placing a group of capacitors that have one terminal connected to a common node.”
Pertinent Art
For the benefits of the Applicant, US 20230410745 A1, US 20180006105 A1, US 20120293496 A1, US 20240355287 A1 are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including the capacitor structure.
Conclusion
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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