DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt on 4 March 2026 of Applicants’ amendments in which the specification is amended, claims 12, 13, and 16-18 are amended, claims 1-11 are cancelled, and claims 21-30 are newly added. The Office withdraws the drawing objection, the section 112(b) rejection, and the section 112(d) rejection identified in the Office Communication dated 5 December 2025 in view of the amendments.
Response to Arguments
Applicants argue in the paragraph bridging 10 and 11 of their Remarks and with respect to independent claim 12 that the references applied in the rejection of 5 December 2025 do not teach the subject matter newly added to claim 12 of “a source and a drain respectively contacting first and second sides of … the third semiconductor layer, wherein … a second channel is contiguous between the second semiconductor layer and the third semiconductor layer.” More specifically, Applicants’ argue Higuchi discloses a "p+-GaN layer 6 providing a gate in each recess" wherein the "recess 8 extends from the surface of the compound semiconductor substrate to reach the lowermost GaN layer 2;” and based upon this argument, Applicants draw the inference that Higuchi fails to disclose a third semiconductor layer contiguous on the second semiconductor layer and a second channel contiguous between the second and third semiconductor layers. Amended claim 12 is rejected over the combined teachings of Shibata, Zhao, Kidera, Weber, and Higuchi. Obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so. MPEP §2143.01. As this principle applies to the present circumstance, the American Heritage College Dictionary, 4th edition, defines the first sense (i.e., most common usage) of “contiguous” as “[s]haring an edge or boundary” and the second sense as “touching.” As may be seen by inspection of Higuchi’s Fig. 5, Higuchi teaches “a source (9) and a drain (10) respectively contacting first (e.g., left) and second (e.g., right) sides of … the third semiconductor layer (e.g., lowermost 4), wherein … a second channel (e.g., channel created by the heterojunction of lowermost AlGaN layer 3 and lowermost GaN layer 4) is contiguous (sharing a boundary or edge; touching) between the second semiconductor layer (e.g., lowermost 3) and the third semiconductor layer (e.g., lowermost 4).” Although not required to achieve the metes and bounds of the claim, Higuchi’s second channel layer has as least the same surface area as does each of Higuchi’s second semiconductor layer and third semiconductor layer within Fig. 5.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1, lines 13-16, recites “the second semiconductor layer is continuous disposed on the first semiconductor layer to connect the source and drain, and the third semiconductor layer is continuous disposed on the second semiconductor layer to connect the source and the drain,” which should read as “the second semiconductor layer is continuously disposed on the first semiconductor layer to connect the source and drain, and the third semiconductor layer is continuously disposed on the second semiconductor layer to connect the source and the drain” for proper grammar and composition.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12-16, 18, 19, and 27-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shibata et al. (US20240313061A1) in view of Zhao et al. (US20240204058A1), Kidera (US20140362626A1), Weber et al. (US20210057576A1), and Higuchi et al. (US20180219086A1).
Regarding claim 12, Shibata teaches in Fig. 1 a semiconductor device comprising:
a substrate (10);
a first semiconductor layer (26) on the substrate (10) and defining a recess;
a second semiconductor layer (28) contiguous on the first semiconductor layer (26);
a third semiconductor layer (32) contiguous on the second semiconductor layer (28);
a gate layer (38) on the third semiconductor layer (32); and
a source (36) contacting a first side of the first semiconductor layer (26) and the second semiconductor layer (28),
wherein a first channel (30) is contiguous between the first semiconductor layer (26) and the second semiconductor layer (28).
Shibata does not necessarily teach the gate layer is a semiconductor.
In an analogous art, Zhao teaches in paragraph [0083] a gate layer is a semiconductor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shibata’s semiconductor device based on the teachings of Zhao – such that Shibata’s gate layer is a semiconductor – to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding gate structure … has different characteristics (e.g., different electron concentrations) than the rest of the 2DEG region and thus is blocked. Due to such mechanism, the bidirectional switching device 100 has a normally-off characteristic. Zhao [0083].
Shibata as modified by Zhao does not necessarily teach a drain contacting a second side of the first semiconductor layer and the second semiconductor layer.
In an analogous art, Kidera teaches in paragraph [0054] a horizontal transistor structure of GaN/AlGaN, in which current flows along an interface of the GaN and AlGaN layers, may replace a vertical transistor structure, in which current flows through laminated semiconductor layers, to reduce electric/heat power loss. In an analogous art, Weber teaches in paragraph [0032] that a horizontal transistor structure has a drain region spaced apart from a source region in a lateral direction of a semiconductor body, whereas a vertical transistor structure has a drain region spaced apart from a source region in a vertical direction of a semiconductor body. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shibata’s semiconductor device as modified by Zhao based on the teachings of Kidera and Weber – such that one of Shibata’s two sources becomes a drain and thereby contacts a second side of Shibata’s first semiconductor layer and second semiconductor layer and thereby transitions Shibata’s vertical transistor structure to a horizontal transistor structure – to reduce electric/heat power loss. Kidera [0054].
Shibata does not necessarily teach:
a source contacting first side of the third semiconductor layer and a drain contacting a second side of the third semiconductor layer,
a second channel is contiguous between the second semiconductor layer and the third semiconductor layer,
the second semiconductor layer is continuous[ly] disposed on the first semiconductor layer to connect the source and drain, and
the third semiconductor layer is continuous[ly] disposed on the second semiconductor layer to connect the source and the drain.
In an analogous art, Higuchi teaches in Fig. 5 and paragraphs [0044] and [0067] a source (9) and a drain (10) respectively contacting first and second sides of a first semiconductor layer (e.g., 2), a second semiconductor layer (e.g., 3 between 2 and 4), and a third semiconductor layer (e.g., lowermost 4), the second semiconductor layer (e.g., 3 between 2 and 4) is continuous[ly] disposed on the first semiconductor layer (e.g., 2) to connect the source (9) and drain (10), and the third semiconductor layer (e.g., lowermost 4) is continuous[ly] disposed on the second semiconductor layer (e.g., 3 between 2 and 4) to connect the source (9) and the drain (10). Higuchi further teaches in paragraph [0067] that a channel is formed at each interface between a GaN layer and an AlGaN layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shibata’s semiconductor device as modified by Zhao, Kidera, and Weber based on the teachings of Higuchi – to include a source contacting first side of the third semiconductor layer and a drain contacting a second side of the third semiconductor layer, wherein a second channel is contiguous between the second semiconductor layer and the third semiconductor layer, the second semiconductor layer is continuous[ly] disposed on the first semiconductor layer to connect the source and drain, and the third semiconductor layer is continuous[ly] disposed on the second semiconductor layer to connect the source and the drain – so an on-resistance is decreased in almost reverse proportion to the number of the 2DEG carrier layers. Higuchi ¶0070.
Regarding claim 13, Shibata as modified by Zhao, Kidera, Weber, and Higuchi teaches the semiconductor device of claim 12, but Shibata does not teach wherein
the source and the drain are spaced apart from each other in a first direction, and
the first semiconductor layer defines a plurality of recesses arranged at intervals in a second direction perpendicular to the first direction, between the source and the drain.
Higuchi teaches in Fig. 5 and paragraph [0041] a source (9) and a drain (10) are spaced apart from each other in a first direction (x direction), and a first semiconductor layer (e.g., 2) defines a plurality of recesses (5) arranged at intervals in a second direction (y direction) perpendicular to the first direction (x direction), between the source (9) and the drain (10). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shibata’s semiconductor device as modified by Zhao, Kidera, Weber, and Higuchi based on the further teachings of Higuchi – such that the source and the drain are spaced apart from each other in a first direction, and the first semiconductor layer includes a plurality of recesses arranged at intervals in a second direction perpendicular to the first direction, between the source and the drain – so a punch through current disenabling the blocking state is restricted from flowing between the drain and the source. Higuchi [0051].
Regarding claim 14, Shibata as modified by Zhao, Kidera, Weber, and Higuchi teaches the semiconductor device of claim 13, but Shibata does not necessarily teach wherein the gate semiconductor layer has a tri-gate structure.
Although neither claim 14 nor Applicants’ specification defines the meaning of a “tri-gate structure,” prospective meanings may include a three-gate structure or a structure in which a recess is gate driven from three sides/planes, as expressed in paragraphs [0044] and [0058] of Applicants’ specification.
Higuchi teaches in Fig. 5 both: (1) a three-gate structure and (2) a structure in which a recess is gate driven from three sides/planes. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shibata’s semiconductor device as modified by Zhao, Kidera, Weber, and Higuchi based on the further teachings of Higuchi – such that the gate semiconductor layer has a tri-gate structure – so a punch through current disenabling the blocking state is restricted from flowing between the drain and the source. Higuchi [0051].
Regarding claim 15, Shibata as modified by Zhao, Kidera, Weber, and Higuchi teaches the semiconductor device of claim 13, but Shibata does not teach wherein the plurality of recesses are apart from adjacent recesses by greater than or equal to about 100 nm and less than or equal to about 1 μm.
Higuchi teaches in Fig. 5 and paragraph a plurality of recesses are apart from adjacent recesses by a distance of 0.5 to 2 μm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shibata’s semiconductor device as modified by Zhao, Kidera, Weber, and Higuchi based on the further teachings of Higuchi – such that the plurality of recesses are apart from adjacent recesses by greater than or equal to about 100 nm and less than or equal to about 1 μm – so a punch through current disenabling the blocking state is restricted from flowing between the drain and the source. Higuchi [0051]. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. MPEP §2144.05(I).
Regarding claim 16, Shibata as modified by Zhao, Kidera, Weber, and Higuchi teaches the semiconductor device of claim 12, but Shibata does not necessarily teach wherein the first and second sides of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are opposite each other.
Higuchi teaches in Fig. 5 and paragraphs [0044] and [0067] that first and second sides of a first semiconductor layer (e.g., 2), a second semiconductor layer (e.g., 3 between 2 and 4), and a third semiconductor layer (e.g., lowermost 4) are opposite each other. The motivation for this modification is identified with respect to base claim 12. Moreover, all the claimed elements (e.g., source, drain, semiconductor layers) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Higuchi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 18, Shibata as modified by Zhao, Kidera, Weber, and Higuchi teaches the semiconductor device of claim 12, and Shibata further teaches wherein a shape of the at least one recess has at least one of an inverted trapezoid, a V-shape or a U-shape {see Examiner’s Note, below}.
Examiner’s Note: Shibata’s recess seems to have an identical shape to that disclosed by Applicants. Specifically, the recess has three surfaces and each pair of adjoining surfaces forms an obtuse angle.
To the extent it may be deemed Applicants’ claimed recess shape differs from that of Shibata’s, a change of shape is a matter of design choice which a person of ordinary skill in the art would have found obvious before the effective filing date of the claimed invention. MPEP §2144.04(IV)(B).
Regarding claim 19, Shibata as modified by Zhao, Kidera, Weber, and Higuchi teaches the semiconductor device of claim 12, but Shibata does not teach further comprising: a fourth semiconductor layer between the third semiconductor layer and the gate semiconductor layer.
Higuchi teaches in Fig. 5 and paragraph [0067] a fourth semiconductor layer (uppermost 3) is disposed over a third semiconductor layer (e.g., lowermost 4). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shibata’s semiconductor device as modified by Zhao, Kidera, Weber, and Higuchi based on the further teachings of Higuchi – such that a fourth semiconductor layer is disposed over the third semiconductor layer – so an on-resistance is decreased in almost reverse proportion to the number of the 2DEG carrier layers. Higuchi ¶0070. A consequence of this modification is that Higuchi’s fourth semiconductor layer is disposed between Higuchi’s third semiconductor layer and Shibata’s modified gate semiconductor layer.
Regarding claim 27, Shibata as modified by Zhao, Kidera, Weber, and Higuchi teaches the semiconductor device of claim 12, but Shibata does not teach wherein the gate semiconductor layer includes p-type GaN.
Zhao teaches in paragraph [0083] the gate semiconductor layer includes p-type III-V compound. GaN is a III-V compound.
Higuchi teaches in Fig. 5 and paragraph [0060] a gate semiconductor layer (6) includes p-type GaN. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shibata’s semiconductor device as modified by Zhao, Kidera, Weber, and Higuchi based on the further teachings of Zhao and Higuchi – such that the gate semiconductor layer includes p-type GaN – to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding gate structure … has different characteristics (e.g., different electron concentrations) than the rest of the 2DEG region and thus is blocked. Due to such mechanism, the bidirectional switching device 100 has a normally-off characteristic. Zhao [0083]. Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 28, Shibata as modified by Zhao, Kidera, Weber, and Higuchi teaches the semiconductor device of claim 12, and Shibata further teaches wherein, the recess is further defined by the second semiconductor layer (28) and the third semiconductor layer (32) {Fig. 1}.
Regarding claim 29, Shibata as modified by Zhao, Kidera, Weber, and Higuchi teaches the semiconductor device of claim 28, and Shibata further teaches wherein, the second semiconductor layer (28) is disposed within the recess on the first semiconductor layer (30) {Fig. 1}.
Regarding claim 30, Shibata as modified by Zhao, Kidera, Weber, and Higuchi teaches the semiconductor device of claim 19, but Shibata does not teach further comprising: a third channel between the fourth semiconductor layer and the third semiconductor layer.
Higuchi teaches in Fig. 5 and paragraphs [0044] and [0067] a third channel between a fourth semiconductor layer (e.g., uppermost 3/uppermost 4) and a third semiconductor layer (e.g., lowermost 4/uppermost 3). Higuchi further teaches in paragraph [0067] that a channel is formed at each interface between a GaN layer and an AlGaN layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shibata’s semiconductor device as modified by Zhao, Kidera, and Weber based on the teachings of Higuchi – to include a third channel between the fourth semiconductor layer and the third semiconductor layer – so an on-resistance is decreased in almost reverse proportion to the number of the 2DEG carrier layers. Higuchi ¶0070.
Claim(s) 17, 21, 22, and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shibata in view of Zhao, Kidera, Weber, and Higuchi as applied to claim 12 (for claim 17), claim 17 (for claims 21 and 22), and claim 18 (for claim 26) above, and further in view of Mishra et al. (US20200119179A1).
Regarding claim 17, Shibata as modified by Zhao, Kidera, Weber, and Higuchi teaches the semiconductor device of claim 12, and Shibata further teaches wherein the at least one recess has a bottom surface (28a) and an inclined side surface (interface between side surfaces of 26 and 28).
Shibata does not teach a thickness of the second semiconductor layer on a side surface of the at least one recess is less than a thickness of the second semiconductor layer on a bottom surface of the at least one recess. However, Shibata teaches in Fig. 1 different thicknesses for the side and bottom surfaces of the second semiconductor layer (28).
In an analogous art, Mishra teaches in Fig. 4 and paragraph [0089] a vertical sidewall of a semiconductor layer (31/32) is a result-effective variable for optimizing both channel mobility and threshold voltage. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the vertical sidewall thickness of Shibata’s second semiconductor layer based on the teachings of Mishra to discover the optimal or workable ranges of a channel mobility and/or threshold voltage such that a thickness of Shibata’s second semiconductor layer on a side surface of the recess is less than a thickness of Shibata’s second semiconductor layer on a bottom surface of the recess.
Regarding claim 21, Shibata as modified by Zhao, Kidera, Weber, Higuchi, and Mishra teaches the semiconductor device of claim 17, but Shibata does not teach wherein, the thickness of the second semiconductor layer on the side surface of the recess is between 2.5nm and 15nm thick; and the thickness of the second semiconductor layer on the bottom surface of the recess is between 5nm and 30nm thick.
However, Shibata teaches in Fig. 1 different thicknesses for the side and bottom surfaces of the second semiconductor layer (28).
Mishra teaches in Fig. 4 and paragraph [0089] a vertical sidewall of a semiconductor layer (31/32) is a result-effective variable for optimizing both channel mobility and threshold voltage. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the vertical sidewall thickness of Shibata’s second semiconductor layer based on the teachings of Mishra to discover the optimal or workable ranges of a channel mobility and/or threshold voltage such that a thickness of Shibata’s second semiconductor layer on the side surface of the recess is between 2.5nm and 15nm thick; and the thickness of Shibata’s second semiconductor layer on the bottom surface of the recess is between 5nm and 30nm thick.
Regarding claim 22, Shibata as modified by Zhao, Kidera, Weber, and Higuchi teaches the semiconductor device of claim 12, but Shibata does not teach wherein, a thickness of the third semiconductor layer on a side surface of the recess is less than a thickness of the third semiconductor layer on a bottom surface of the recess.
However, Shibata teaches in Fig. 1 different thicknesses for the side and bottom surfaces of the third semiconductor layer (32).
Mishra teaches in Fig. 4 and paragraph [0089] a vertical sidewall of a semiconductor layer (31/32) is a result-effective variable for optimizing both channel mobility and threshold voltage. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the vertical sidewall thickness of Shibata’s third semiconductor layer based on the teachings of Mishra to discover the optimal or workable ranges of a channel mobility and/or threshold voltage such that a thickness of Shibata’s third semiconductor layer on a side surface of the recess is less than a thickness of the third semiconductor layer on a bottom surface of the recess.
Regarding claim 26, Shibata as modified by Zhao, Kidera, Weber, and Higuchi teaches the semiconductor device of claim 18, but Shibata does not teach wherein: a thickness of the second semiconductor layer on a side surface of the at least one recess is less than a thickness of the second semiconductor layer on a bottom surface of the at least one recess.
However, Shibata teaches in Fig. 1 different thicknesses for the side and bottom surfaces of the second semiconductor layer (28).
Mishra teaches in Fig. 4 and paragraph [0089] a vertical sidewall of a semiconductor layer (31/32) is a result-effective variable for optimizing both channel mobility and threshold voltage. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the vertical sidewall thickness of Shibata’s second semiconductor layer based on the teachings of Mishra to discover the optimal or workable ranges of a channel mobility and/or threshold voltage such that a thickness of Shibata’s second semiconductor layer on a side surface of the recess is less than a thickness of Shibata’s second semiconductor layer on a bottom surface of the recess.
Claim(s) 20 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shibata in view of Zhao, Kidera, Weber, and Higuchi as applied to claim 12 (for claim 20) and claim 19 (for claim 23) above, and further in view of Zhang et al. (US20240079484A1).
Regarding claim 20, Shibata as modified by Zhao, Kidera, Weber, and Higuchi teaches the semiconductor device of claim 12, but Shibata does not teach further comprising: a passivation layer covering the third semiconductor layer and the gate semiconductor layer.
In an analogous art, Zhang teaches in Fig. 8 and paragraph [0054] a passivation layer (118) covering a third semiconductor layer (a GaN or an AlGaN layer of 108) and a gate semiconductor layer (126). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shibata’s semiconductor device as modified by Zhao, Kidera, Weber, and Higuchi based on the teachings of Zhang – such that a passivation layer covers the third semiconductor layer and the gate semiconductor layer – to insulate the underlying structure for external environmental electrical signals. Zhang [0054]. Moreover, all the claimed elements (e.g., passivation layer, semiconductor layers) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Zhang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 23, Shibata as modified by Zhao, Kidera, Weber, and Higuchi teaches the semiconductor device of claim 19, but Shibata does not teach further comprising: a passivation layer covering the fourth semiconductor layer and the gate semiconductor layer.
Zhang teaches in Fig. 8 and paragraph [0054] a passivation layer (118) covering a fourth semiconductor layer (a GaN or an AlGaN layer of 108) and a gate semiconductor layer (126). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shibata’s semiconductor device as modified by Zhao, Kidera, Weber, and Higuchi based on the teachings of Zhang – such that a passivation layer covers the fourth semiconductor layer and the gate semiconductor layer – to insulate the underlying structure for external environmental electrical signals. Zhang [0054]. Moreover, all the claimed elements (e.g., passivation layer, semiconductor layers) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Zhang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 24 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shibata in view of Zhao, Kidera, Weber, and Higuchi as applied to claim 12 above, and further in view of Soman et al. (US20200227543A1).
Regarding claim 24, Shibata as modified by Zhao, Kidera, Weber, and Higuchi teaches the semiconductor device of claim 12, but Shibata does not teach wherein the at least one recess further comprises ions, the ions including at least one of Ar, F, B, or Mg.
In an analogous art, Soman teaches in Fig. 8 and paragraph [0064] a recess (recess below 410 in 412a) further comprises F ions (702). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shibata’s semiconductor device as modified by Zhao, Kidera, Weber, and Higuchi based on the teachings of Soman – such that the at least one recess further comprises ions, the ions including at least one of Ar, F, B, or Mg – to fabricate normally-OFF AlGaN/GaN HEMT. Soman [0004].
Regarding claim 25, Shibata as modified by Zhao, Kidera, Weber, Higuchi, and Soman teaches the semiconductor device of claim 24, but Shibata does not teach wherein, the source and the drain are spaced apart from each other in a first direction, and the first semiconductor layer includes a plurality of recesses arranged at intervals in a second direction perpendicular to the first direction, between the source and the drain.
Higuchi teaches in Fig. 5 and paragraph [0041] a source (9) and a drain (10) are spaced apart from each other in a first direction (x direction), and a first semiconductor layer (e.g., 2) includes a plurality of recesses (5) arranged at intervals in a second direction (y direction) perpendicular to the first direction (x direction), between the source (9) and the drain (10). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shibata’s semiconductor device as modified by Zhao, Kidera, Weber, Higuchi, and Soman based on the further teachings of Higuchi – such that the source and the drain are spaced apart from each other in a first direction, and the first semiconductor layer includes a plurality of recesses arranged at intervals in a second direction perpendicular to the first direction, between the source and the drain – so a punch through current disenabling the blocking state is restricted from flowing between the drain and the source. Higuchi [0051].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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