Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species VII, Figs. 21-25A and 26, in the reply filed on 04/21/2026 is acknowledged. Claims 7-8 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim, and election was made without traverse in the amendment filed on 04/21/2026.
Therefore, claims 1-6 and 9-20 have been fully considered in examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 and 9-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ),
second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject
matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the
applicant), regards as the invention.
Claim 1 recites “a second etch rate….is different than the first etch rate,” but does not specify the direction of the difference. Since the direction controls the resulting structure, the claim scope is unclear: a faster middle portion recesses more deeply (central protrusion), while a slower middle portion produces the opposite profile.
Claims 2-6 and 9-20 are also rejected being dependent on rejected claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lue (US 10,403,637 B2) in view of Choi (US 7,988,875 B2).
Regarding Claim 1, Lue teaches a method of forming a memory device comprising:
forming a vertical repetition of a unit layer stack comprising an insulating layer and a sacrificial material layer (forming stacks of sacrificial strips, e.g., silicon nitride, alternating with insulating strips, FIG. 12, Step 1; FIG. 18, Step 1811);
forming a memory opening having a straight sidewall through the vertical repetition (forming stacks/trenches having sidewalls, FIG. 12);
laterally recessing the sacrificial material layers selective to the insulating layers to form lateral recesses (recessing the first sidewalls of the sacrificial strips relative to the sides of the insulating strips by isotropic etching to define recessed regions, FIG. 3; FIG. 12, Step 2);
forming a memory opening fill structure comprising a vertical stack of memory elements that are formed in the lateral recesses, a dielectric material liner, and a vertical semiconductor channel (forming data storage structures having discrete charge trapping elements disposed in the recessed regions, with tunneling layers and vertical channel films, FIG. 12, Step 3–4; FIGS. 8–9; FIG. 18, Step 1813–1814); and
replacing the sacrificial material layers with electrically conductive layers (replacing the sacrificial strips with a metal material such as tungsten, FIGS. 13–17; FIG. 18, Step 1816).
Lue does not teach that the sacrificial material layer is a composite sacrificial material layer having a vertical compositional change that is stepwise or gradual such that a bottommost portion and a topmost portion have a first etch rate in an isotropic etchant, and a middle portion has a second etch rate that is different than the first etch rate.
However, Choi teaches a composite silicon nitride material layer having a compositional change such that a first portion has a first etch rate and a second portion has a second etch rate different than the first etch rate, the compositional change being produced by depositing silicon nitride from a nitrogen-containing precursor at different flow rates (Choi col.2:55-67; claim 1, col.20:36-51). Choi further teaches that the compositional change may be stepwise (discrete sub-layers, Choi col.6:1-17;Fig. 3A) or gradual (in-situ adjustment of the precursor flow rate during deposition to form graduated composition layering structures, Choi col.10:1-6).
It would have been obvious to one of ordinary skill in the art before the effective filing date to form Lue's sacrificial silicon nitride layer as Choi's composite layer having vertically varying etch rates, in order to control the lateral recess depth at different vertical levels. The etch rate of silicon nitride is a result-effective variable, and optimizing it through compositional control is within the level of ordinary skill. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
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Regarding claim 2, Lue in view of Choi teaches the method of Claim 1, wherein the first etch rate is greater than the second etch rate (etch rate of each silicon nitride sub-layer is set by the precursor flow rate during deposition, Choi col.7:1–13; selecting which portion is given the higher etch rate is a routine design choice).
Regarding claim 3, Lue in view of Choi teaches the method of Claim 2, wherein the lateral recesses have a straight vertical outer sidewall, and the memory elements have a straight outer vertical sidewall facing the electrically conductive layers (Lue, recessed regions defined by isotropic etching with the discrete charge trapping elements disposed therein, FIG. 3; FIG. 12).
Regarding claim 4, Lue in view of Choi teaches the method of claim 3, wherein the vertical stack of memory elements comprises a vertical stack of discrete memory elements (Lue, discrete charge trapping elements separated from one another in the vertical direction, FIGS. 6–7, 10; FIG. 12).
Regarding claim 5, Lue in view of Choi teaches the method of claim 4, wherein the discrete memory elements have a straight inner sidewall facing the vertical semiconductor channel (Lue, discrete charge trapping elements in contact with the tunneling layers along the vertical channel films, FIG. 8; FIG. 12).
Regarding claim 6, Lue in view of Choi teaches the method of claim 5, wherein discrete memory elements comprise discrete silicon nitride charge storage elements (Lue, discrete charge trapping elements comprising silicon nitride (SiN), FIG. 5; FIG. 12).
Regarding claim 9, Lue in view of Choi teaches the method of Claim 3, wherein the electrically conductive layers have a straight inner sidewall facing the straight outer vertical sidewall of the memory elements (Lue, conductive/metal strips replacing the sacrificial strips and bounding the recessed regions in which the discrete charge trapping elements are disposed, FIGS. 13–17; FIG. 12).
Regarding claim 10, Lue in view of Choi teaches the method of claim 9, wherein the memory opening fill structure further comprises a blocking dielectric layer in contact with an entirety of the outer sidewalls of the vertical stack of memory elements (Lue, blocking layers between the discrete charge trapping elements and the sidewalls of the conductive strips, FIG. 4; FIG. 12).
Regarding claim 11, Lue in view of Choi teaches the method of claim 10, wherein the blocking dielectric layer has straight outer vertical sidewalls located in the lateral recesses and facing the straight inner sidewalls of the electrically conductive layers (Lue, blocking layers disposed in the recessed regions between the discrete charge trapping elements and the conductive strips, FIG. 4; FIG. 12).
Regarding claim 12, Lue in view of Choi teaches the method of Claim 1, wherein:
the memory elements comprise charge storage elements (Lue, discrete charge trapping elements as charge storage, FIG. 1);
the dielectric material liner comprises a tunneling dielectric layer (Lue, tunneling layers as the dielectric liner, FIG. 1); and
the memory device comprises a vertical NAND string (Lue, in a 3D vertical-channel NAND device, FIG. 1).
Regarding claim 13, Lue in view of Choi teaches the method of Claim 1, wherein the middle portion comprises a first silicon nitride material, and the topmost and bottommost portions comprise a second silicon nitride material having at least one of a different porosity or different silicon-to-nitrogen ratio than the first silicon nitride material (Choi teaches depositing first and second silicon nitride layers having differential etch rates by changing the nitrogen-containing precursor amount, where a lower wet etch rate corresponds to a denser layer, such that the resulting compositional/density difference is inherent, Choi col.9:3–28; col.5:40–42; In re Best, 562 F.2d 1252, 1254, 195 USPQ 430, 433 (CCPA 1977)).
Regarding claim 14, Lue in view of Choi teaches the method of Claim 13, wherein each composite sacrificial material layer has a vertical compositional profile that changes stepwise (Choi teaches sequentially depositing discrete first and second silicon nitride layers, Choi col.6:1–17; FIG. 3A).
Regarding claim 15, Lue in view of Choi teaches the method of Claim 14, wherein the bottommost portion comprises a first silicon nitride layer, the middle portion comprises a second silicon nitride layer, and the topmost portion comprises a third silicon nitride layer (Choi teaches that two or more layers may be deposited, e.g., a three-layer stack in which the first and third layers have the same etch rate, Choi col.9:62–67).
Regarding claim 16, Lue in view of Choi teaches the method of Claim 13, wherein each composite sacrificial material layer comprises a compositionally-graded silicon nitride layer in which a porosity or silicon-to-nitrogen ratio gradually changes (Choi teaches continuous deposition with changing precursor flow rates to form graduated composition layering structures with smooth transitions between material layers, Choi col.10:1–6; col.5:7–13).
Regarding claim 17, Lue in view of Choi teaches the method of Claim 13, wherein the isotropic etchant comprises a wet etch solution comprising hot phosphoric acid (Choi teaches wet etching of the silicon nitride dual layer, col.5:36–42; hot phosphoric acid is art-recognized as suitable for selectively removing silicon nitride, MPEP 2144.07).
Regarding claim 18, Lue in view of Choi teaches the method of Claim 13, wherein the isotropic etchant comprises a wet etch solution including a mixture of hydrofluoric acid and ethylene glycol (Choi teaches a hydrofluoric-acid-based wet etch solution, e.g., 6:1 BOE, Choi col.5:37–40; an HF-based etchant mixture being functional equivalent recognized in the art for etching silicon nitride, MPEP 2144.06).
Regarding claim 19, Lue in view of Choi teaches the method of Claim 13, wherein the isotropic etchant comprises a wet etch solution including a mixture of hydrofluoric acid and nitric acid (Choi teaches a hydrofluoric-acid-based wet etch solution, e.g., 6:1 BOE, Choi col.5:37–40; an HF-based etchant mixture being functional equivalent recognized in the art for etching silicon nitride, MPEP 2144.06).
Regarding claim 20, Lue in view of Choi teaches the method of Claim 1, wherein the memory opening fill structure further comprises a drain region located in contact with an upper portion of the vertical semiconductor channel (Lue teaches a drain/bit-line region contacting the upper end of the vertical channel of the NAND string, Lue FIG. 1; FIG. 12).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAHAE KIM whose telephone number is (571)270-1844. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on (571) 271-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JAHAE KIM/Examiner, Art Unit 2897
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