Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election of claims 1 – 15 without traverse, in the reply filed on 1/28/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1–6, 8-13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hausmann ( Pub. No. US 20190157076 A1 ), hereinafter Hausmann, in view of Yang ( Pub. No. US 20080254624 A1 ), hereinafter Yang.
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Regarding Independent Claim 1, Hausmann teaches a structure, comprising:
semiconductor devices ( Hausmann, [0001], Semiconductor device; [0047], one or more layers of material, such as dielectric, conducting, or semi-conducting material deposited thereon ) located over a substrate ( Hausmann, FIG. 2A, 201; [0037], dielectric substrate 201; [0047], a substrate having an exposed copper surface and an exposed dielectric surface is provided );
a first interconnect-level dielectric layer ( Hausmann, FIG. 2A, 201; [0037], dielectric substrate 201 ) located above the semiconductor devices;
a first metal structure ( Hausmann, FIG. 2A, 203a, 203b; [0037], a dielectric substrate 201 includes copper vias 203a and 203b ) embedded in the first interconnect-level dielectric layer ( Hausmann, FIG. 2A, 201 ), wherein a top surface of the first metal structure ( Hausmann, FIG. 2A, 203a, 203b ) and a top surface of the first interconnect-level dielectric layer (Hausmann, FIG. 2A, 201) are located in a same first horizontal plane ( Hausmann, [0038], a dual damascene structure planarized by CMP to expose the metal in the via, followed by selective deposition of dielectric material on dielectric material relative to metal in the via );
a spacer dielectric material layer ( Hausmann, FIG. 2B, 213; [0037], dielectric material 213 is deposited selectively on the dielectric 201 surfaces relative to the exposed copper surfaces of copper vias 203a and 203b ) having a contoured top surface and a planar bottom surface located in the first horizontal plane ( Hausmann, [0038], planarized by CMP ) on the top surface of the first interconnect-level dielectric layer ( Hausmann, FIG. 2A, 201 );
at least one opening ( Hausmann, FIG. 2B, opening between213; [0041], utilizing the reactivity difference between that of hydroxyl-terminated silicon oxide and of reduced copper to allow selective deposition using exposure to a copper-blocking reagent, such as a thiol, which preferentially adsorbs to the reduced copper surface and blocks subsequent deposition on the copper surface ) located in the spacer dielectric material layer ( Hausmann, FIG. 2B, 213 );
the at least one opening ( Hausmann, FIG. 2B, opening between213 ) and at least a portion of the top surface of the first metal structure ( Hausmann, FIG. 2A, 203a, 203b ); and
a second metal structure ( Hausmann,FIG. 2F, copper is filled into the vias 235; [0037], Since the selectively deposited dielectric material 213 has etch selectivity to the ULK dielectric material 231, the vias 235 are fully self-aligned. In FIG. 2F, copper is filled into the vias to form the dual damascene structure ).
Hausmann does not explicitly disclose:
a metal cap structure located in the at least one opening and having a bottom surface in contact with at least a portion of the top surface of the first metal structure; and
a second metal structure located on a top surface of the metal cap structure.
However, Yang teaches:
a metal cap structure ( Yang , FIG. 10, metal cap 121 ) located in the at least one opening and having a bottom surface in contact ( Yang, [0036], metal cap 121 having portions 122a and 122b covering conductive metal 112 ) with at least a portion of the top surface of the first metal structure; and
a second metal structure ( Yang, FIG. 10, 128A, [0039], dual damascene line 128A ) located on a top surface of the metal cap structure ( Yang , FIG. 10, metal cap 121 ).
Hausmann and Yang are both considered to be analogous to the claimed invention because they are forming selective deposition processes for SiO2 and metal. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hausmann ( Hausmann, FIG. 2E, FIG. 2F ), to incorporate the teachings of Yang ( FIG. 10, metal cap 121 ), to implement that a metal cap structure ( Yang , FIG. 10, metal cap 121 ) located in the at least one opening ( Hausmann, FIG. 2E, vias 235 ) and having a bottom surface in contact with at least a portion of the top surface of the first metal structure ( Hausmann, FIG. 2A, 203a, 203b ); and a second metal structure ( Hausmann,FIG. 2F, copper is filled into the vias 235 ) located on a top surface of the metal cap structure ( Yang , FIG. 10, metal cap 121 ). Doing so would provide specific selective deposition processes for SiO2 and metal, and therefore the self-alignment for metal interconnections can be improved.
Regarding Claim 2, Hausmann and Yang teach the structure as claimed in Claim 1, on which this claim is dependent, Hausmann and Yang further teach: wherein:
the first interconnect-level dielectric layer ( Hausmann, FIG. 2A, 201 ) comprises a line-level dielectric layer ( Hausmann, [0048], the substrate includes a dielectric material and vias filled with a metal (such as interconnect lines) );
the first metal structure ( Hausmann, FIG. 2A, 203a, 203b ) comprises metal lines embedded in the line-level dielectric layer ( Hausmann, FIG. 2A, 201; [0048], the substrate includes a dielectric material ), laterally spaced apart from each other along a first horizontal direction that is a widthwise direction of the metal lines (), and laterally extending along a second horizontal direction that is a lengthwise direction of the metal lines ( Hausmann, FIG. 2A, 203a, 203b );
the contoured top surface of the spacer dielectric material layer ( Hausmann, FIG. 2B, 213 ) has edges located on top surfaces of a respective neighboring pair of the metal lines ( Hausmann, FIG. 2A, 203a, 203b ); and
the second metal structure ( Hausmann,FIG. 2F, copper is filled into the vias 235 ) comprises a metal via structure ( Yang, FIG. 10, 128A, [0039], dual damascene line 128A includes a contact via extending through second dielectric layer 108 and dielectric capping layer 106 for connecting with interconnect element 104 ) contacting a top surface of the metal cap structure ( Yang , FIG. 10, metal cap 121 ).
Regarding Claim 3, Hausmann and Yang teach the structure as claimed in Claim 2, on which this claim is dependent, Hausmann further teaches: wherein:
the contoured surface ( Hausmann, FIG. 2B, 213; [0037], dielectric material 213 is deposited selectively on the dielectric 201 surfaces ) comprises a planar horizontal surface segment ( Hausmann, FIG. 2B, bottom surface of 213; [0038], planarized by CMP ) and a pair of convex surface segments ( Hausmann, FIG. 2B, left, top, and right surfaces of 213 ) that are adjoined to the planar horizontal surface segment ( Hausmann, FIG. 2B, bottom surface of 213; [0038], planarized by CMP ); and
the edges of the contoured top surface comprise the edges of the pair of convex surface segments ( Hausmann, FIG. 2B, left, top, and right surfaces of 213 ) that laterally extend along the second horizontal direction.
Regarding Claim 4, Hausmann and Yang teach the structure as claimed in Claim 2, on which this claim is dependent, Hausmann further teaches:
further comprising a via-level dielectric layer ( Hausmann, FIG. 2C, 211; FIG. 2F, 231; [0037], In FIG. 2C, blanket ULK dielectric material 211 is deposited over the substrate that includes the dielectric material 213, and copper vias 203a and 203b; … In FIG. 2E, the blanket ULK dielectric material is further etched to form etched ULK dielectric material 231 ) that overlies the line-level dielectric layer ( Hausmann, FIG. 2A, 201; [0048], the substrate includes a dielectric material ) and the spacer dielectric material ( Hausmann, FIG. 2B, 213 ) portions, wherein the metal via structure ( Hausmann,FIG. 2F, copper is filled into the vias 235 ) is embedded in the via-level dielectric layer (Hausmann, FIG. 2F, 231).
Regarding Claim 5, Hausmann and Yang teach the structure as claimed in Claim 2, on which this claim is dependent, Yang further teaches:
wherein the metal cap structure ( Yang , FIG. 10, metal cap 121 ) has a contoured top surface ( Yang , FIG. 10, V-shaped metal cap 121 ) which has a periphery that coincides with a periphery of a contoured bottom surface ( Yang, FIG. 10, V-shaped of 128A ) of the metal via structure ( Yang, FIG. 10, 128A; [0039], dual damascene line 128A includes a contact via ).
Regarding Claim 6, Hausmann and Yang teach the structure as claimed in Claim 5, on which this claim is dependent, Yang further teaches: wherein:
wherein the contoured top surface of the metal cap structure ( Yang , FIG. 10, metal cap 121 ) comprises a horizontal surface segment within an area ( Yang, FIG. 10, the center region of metal cap 121, i.e. the V-contact region ) that does not have any areal overlap with the spacer dielectric material layer ( Yang, FIG. 10, 106; [0028], dielectric capping layer 106 ) in a plan view, and comprises a convex surface segment within an area ( Yang, FIG. 10, 122a, 122b; [0039], overhang portions 122a and 122b formed between interconnect element 104 and dielectric capping layer 106 ) that has an areal overlap with the spacer dielectric material layer ( Yang, FIG. 10, 106; [0028], dielectric capping layer 106 ).
Regarding Claim 8, Hausmann and Yang teach the structure as claimed in Claim 1, on which this claim is dependent, Hausmann and Yang further teach: wherein:
the first interconnect-level dielectric layer ( Hausmann, FIG. 2A, 201 ) comprises a via-level dielectric layer ( Hausmann, [0037], dielectric substrate 201 );
the first metal structure ( Hausmann, FIG. 2A, 203a, 203b ) comprises a metal via structure ( Hausmann, [0037], copper vias 203a and 203b );
the spacer dielectric material layer ( Hausmann, FIG. 2B, 213 ) covers a peripheral segment of a top surface of the metal via structure ( Hausmann, FIG. 2A, copper vias 203a and 203b ) without covering a center segment of a top surface of the metal via structure ( Hausmann, FIG. 2A, copper vias 203a and 203b ) that is located within an area of the at least one opening ( Hausmann, FIG. 2B, opening between 213; [0041], such as a thiol, which preferentially adsorbs to the reduced copper surface and blocks subsequent deposition on the copper surface );
the second metal structure ( Hausmann, FIG. 2F, copper is filled into the vias 235 ) comprises metal lines overlying the spacer dielectric material layer ( Hausmann, FIG. 2B, 213 ), laterally spaced apart from each other along a first horizontal direction that is a widthwise direction of the metal lines, and laterally extending along a second horizontal direction that is a lengthwise direction of the metal lines ( Hausmann, , [0038], line trench etch whereby etch contrast provides self-alignment, followed by dual damascene metal fill ); and
the metal cap structure ( Yang , FIG. 10, metal cap 121 ) contacts a bottom surface of a first metal line of the metal lines ( Yang , FIG. 10, dual damascene line 128A ), and contacts an entirety of a periphery of the at least one opening in the contoured top surface ( Yang , [0039], Metal cap 121 is embedded therebetween with overhang portions 122a and 122b formed between interconnect element 104 and dielectric capping layer 106 ).
Regarding Claim 9, Hausmann and Yang teach the structure as claimed in Claim 8, on which this claim is dependent, Hausmann further teaches: wherein:
wherein the contoured top surface comprises a planar horizontal surface segment and a convex surface segment that is adjoined to the periphery of the at least one opening and that overlies an outer portion of the top surface of the metal via structure ( Hausmann, FIG. 2B, 213; selectively deposited dielectric material 213 having a planar horizontal surface segment over the dielectric 201 and a convex surface segment adjoined to the periphery of the opening and overlying the outer portion of the copper via 203a ).
Regarding Claim 10, Hausmann and Yang teach the structure as claimed in Claim 9, on which this claim is dependent, Yang further teaches: wherein:
wherein the metal cap structure ( Yang , FIG. 10, metal cap 121 ) comprises a tapered concave sidewall ( Yang, FIG. 5, 119, 117a, 117b; [0034], opposing sides 117a and 117b which extend into interconnect element 104 to an end 119 ) having a flare-shaped ( Yang, FIG. 6, 118a, 118b; [0035], undercut areas 118a and 118b ) vertical cross-sectional profile such that a bottom surface of the metal cap structure has a lesser lateral extent than a top surface of the metal cap structure ( Yang , FIG. 7, metal cap 121; [0034], via gauging feature 116 includes opposing sides 117a and 117b; [0035], undercut areas 118a and 118b, resulting in the metal cap 121 having a flare-shaped vertical cross-sectional profile with a narrower bottom end 119 ).
Regarding Claim 11, Hausmann and Yang teach the structure as claimed in Claim 8, on which this claim is dependent, Yang further teaches:
wherein the metal cap structure ( Yang , FIG. 10, metal cap 121 ) has a contoured top surface which has a periphery that does not coincide with a bottom edge of the first metal line ( Yang , FIG. 10, metal cap 121; overhang portions 122a and 122b of metal cap 121 extend laterally into the undercut areas under the dielectric, thus the periphery does not coincide with the bottom edge of the upper dual damascene line 128A ).
Regarding Claim 12, Hausmann and Yang teach the structure as claimed in Claim 8, on which this claim is dependent, Yang further teaches:
further comprising a line-level dielectric layer ( Yang, FIG. 10, 106, 108; [0028], dielectric layers 106 … second insulating layer 108 ) which embeds the metal lines ( Yang , FIG. 10, dual damascene line 128A ), wherein the metal cap structure ( Yang , FIG. 10, metal cap 121, metal layer 120 ) is in direct contact with the line-level dielectric layer ( Yang , FIG. 10, metal cap 121; [0036], forming an undercut area adjacent to the interconnect feature and the dielectric capping layer, resulting in the metal cap structure 121 being in direct contact with the surrounding dielectric layers 106 and 108 ).
Regarding Claim 13, Hausmann and Yang teach the structure as claimed in Claim 8, on which this claim is dependent, Hausmann further teaches: wherein:
the first metal line ( Hausmann, FIG. 1E, metal in 109; [0036], In FIG. 1E, the via 109 is filled with metal to connect to the metal line 103a. However, as a result of the misalignment of via 109, deposition of the metal into the via 109 may penetrate into the substrate material 101, causing the formation of what is referred to as a “fang” or “tiger tooth” defect 111 ) has a first bottom edge ( Hausmann, FIG. 1E, “bottom metal in 109” which contacts 103a ) and a second bottom edge ( Hausmann, FIG. 1E, “bottom metal in 109” which is filled in 111, and does not contact 103a ) that laterally extend along the second horizontal direction;
Hausmann and Yang do not explicitly disclose:
the first bottom edge contacts the metal cap structure; and
the second bottom edge that does not contact the metal cap structure.
However, Hausmann teaches that lithographic misalignment occurs during interconnect formation, causing an unlanded via structure and forming a fang or tiger tooth defect 111 (Hausmann, FIG. 1D, FIG. 1E, 109, 111). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to recognize that the combined structure of Hausmann ( Hausmann, FIG. 1E, “bottom metal in 109” which contacts or does not contact 103a ) and Yang ( Yang , FIG. 10, metal cap 121 ) can make one edge of the upper metal contacting the metal cap and the opposite edge contacting the dielectric material and not contacting the metal cap. Doing so is merely the natural physical result of misalignment during interconnect formation explicitly disclosed by Hausmann.
Regarding Claim 15, Hausmann and Yang teach the structure as claimed in Claim 1, on which this claim is dependent, Hausmann further teaches: wherein:
wherein the spacer dielectric material layer comprises silicon oxide carbide ( [0040], selectively depositing dielectric material on dielectric material relative to copper, copper oxides, ruthenium, and/or ruthenium oxides. For example, disclosed embodiments may involve depositing silicon oxide (e.g., SiO2) on silicon oxide (SiO2), aluminum oxide (Al2O3), silicon oxycarbides, silicon carbonitrides, and silicon oxycarbonitrides. A non-limiting example of a silicon oxycarbide is a silicon oxycarbide having the chemical formula SiOxCy where 2x+4y=4 (x and y need not be integers). ).
Claims 7, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Hausmann, in view of Yang, in view of Kai ( Pub. No. US 20200258904 A1 ), hereinafter Kai.
Regarding Claim 7, Hausmann and Yang teach the structure as claimed in Claim 2, on which this claim is dependent;
Hausmann and Yang do not explicitly disclose:
the semiconductor devices comprise three dimensional memory devices comprising a vertical semiconductor channel and a memory film;
the metal lines comprise bit lines of the three dimensional memory devices; and
a peripheral circuit is located on a second substrate in a logic die is bonded to a memory die containing three dimensional memory devices.
However, Kai teaches:
the semiconductor devices comprise three dimensional memory devices ( Kai, Abstract, three-dimensional memory device ) comprising a vertical semiconductor channel ( Kai, [0072], vertical semiconductor channel 60 ) and a memory film ( Kai, [0072], memory film 50 );
the metal lines comprise bit lines ( Kai, [0095], The bit lines 98 are electrically connected to upper ends of a respective subset of the vertical semiconductor channels 60 ) of the three dimensional memory devices ( Kai, Abstract, three-dimensional memory device ); and
a peripheral circuit ( Kai, [0097], The semiconductor devices 710 includes a peripheral circuitry ) is located on a second substrate in a logic die ( Kai, [0097], a logic die 700 including various semiconductor devices 710 ) is bonded to a memory die ( Kai, [0096], The memory die 1000 includes a three-dimensional array of memory elements; [0097], The semiconductor devices 710 includes a peripheral circuitry for operation of the three-dimensional memory arrays in the memory die 1000 ) containing three dimensional memory devices ( Kai, Abstract, three-dimensional memory device ).
Hausmann, Yang and Kai are all considered to be analogous to the claimed invention because they are forming semiconductor devices and metal interconnections, including selective deposition processes. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hausmann ( Self-alignment for metal interconnections, FIG. 2A – 2F ) and Yang ( metal cap, FIG. 10 ), to incorporate the teachings of Kai ( bonded 3D memory devices , FIG. 15 – 16), to implement that the semiconductor devices comprise three dimensional memory devices comprising a vertical semiconductor channel and a memory film; the metal lines comprise bit lines of the three dimensional memory devices; and a peripheral circuit is located on a second substrate in a logic die is bonded to a memory die containing three dimensional memory devices. Doing so would provide that the self-alignment for metal interconnections to be used in bonded 3D memory devices, and therefore the metal interconnections performance and integration density can be improved for bonded 3D memory devices.
Regarding Claim 14, Hausmann, Yang and Kai teach the structure as claimed in Claim 8, on which this claim is dependent; Kai further teaches: wherein:
the semiconductor devices comprise three dimensional memory devices ( Kai, Abstract, three-dimensional memory device ) comprising a vertical semiconductor channel ( Kai, [0072], vertical semiconductor channel 60 ) and a memory film ( Kai, [0072], memory film 50 );
the metal lines comprise bit lines ( Kai, [0095], The bit lines 98 are electrically connected to upper ends of a respective subset of the vertical semiconductor channels 60 ) of the three dimensional memory devices ( Kai, Abstract, three-dimensional memory device ); and
a peripheral circuit ( Kai, [0097], The semiconductor devices 710 includes a peripheral circuitry ) is located on a second substrate in a logic die ( Kai, [0097], a logic die 700 including various semiconductor devices 710 ) is bonded to a memory die ( Kai, [0096], The memory die 1000 includes a three-dimensional array of memory elements; [0097], The semiconductor devices 710 includes a peripheral circuitry for operation of the three-dimensional memory arrays in the memory die 1000 ) containing three dimensional memory devices ( Kai, Abstract, three-dimensional memory device ).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817