DETAILED ACTION
This Office Action is in response to Application filed July 5, 2023.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species C drawn to the embodiment shown in Fig. 3 of current application and Subspecies e drawn to the embodiment shown in Fig. 5 of current application in the reply filed on October 23, 2025 is acknowledged. In addition, Applicants’ election without traverse of Species I drawn to the embodiment having a feature recited in claim 5 in the reply filed on March 5, 2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. It is not clear what the limitation “the buffer layer completely fills the plurality of recesses” recited on lines 1-2 refers to, because (a) as recited in claims 16 and 18, the buffer layer comprises a group III nitride material, and the growth substrate comprises silicon, (b) however, as Fig. 2-12, 14, 15, 18 and 24 of Brueck et al. (US 10,453,996) show, actual GaN-based semiconductor materials deposited on recessed Si-based substrates would not completely and directly cover the underlying, exposed surfaces of the Si-based substrates due to their different crystalline structures and different lattice constants as well as different atomic sizes of the constituent elements and surface roughness of the underlying Si-based substrates with steps and terraces, (c) it appears that the claim limitation cited above is derived from the feature illustrated in Fig. 3 of current application, but Fig. 3 of current application is a mere schematic illustration that does not represent an actual structure down to the atomic levels and does not show any detailed structures of the buffer layer and the growth substrate, while Brueck et al. show actual structures of GaN-based semiconductor materials deposited on recessed Si-based substrates, (d) the group III nitride material constituting the buffer layer is a solid material, and therefore, once deposited, the group III nitride material cannot be modified to conform to the surface profiles of the underlying growth substrate, (e) therefore, it is not clear how the limitation “the buffer layer completely fills the plurality of recesses” is defined unambiguously, and (f) it is not clear whether all of the bottommost atoms constituting the buffer layer are bonded to all of the exposed atoms constituting the growth substrate, which is not actually and physically possible since the atomic size of the silicon atoms are different from the atomic sizes of group III element atoms and nitrogen atoms constituting the buffer layer, and it is not clear whether there should not be a void or cavity larger than a certain, unspecified size to be referred to be a configuration where “the buffer layer completely fills the plurality of recesses”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 7, 8 and 15-18 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Chen (US 11,127,848)
In the below prior art rejection, the claim limitations “growth substrate” and “buffer layer” specify intended uses or fields of use, because (a) the “growth substrate” 301/302 in Fig. 3 of current application is basically a patterned silicon layer of a silicon-on-insulator substrate for growing GaN-based semiconductor materials, and (b) the “buffer layer” 4 in Fig. 3 of current application is a buffer layer and also a channel layer of a high electron mobility transistor, and are treated as non-limiting since it has been held that in device claims, intended use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex Parte Masham, 2 USPQ 2d 1647 (Bd. Pat. App. & Inter. 1987).
Regarding claim 1, Chen discloses a semiconductor structure (Fig. 6 or 7), comprising: a supporting substrate (111), a buried layer (112), a growth substrate (composite structure of 113 and 120), because a GaN-based semiconductor buffer layer 131 is grown on the composite structure of 113 and 120 just like Applicants’ growth substrate 301/302 in Fig. 3 of current application, a buffer layer (131, which is composite layer of 131A and 131B) (col. 5, line 60), and a heterojunction structure layer (composite layer of 132 and 133, or composite layer of 132-134) (col. 5, lines 60-62, and col. 7, lines 13-15) that are sequentially stacked, wherein a plurality of recesses (114; trenches) are disposed on a side, away from the supporting substrate, of the growth substrate, and the buffer layer completely covers a surface of the growth substrate (top surface of 113 and 120), because (a) the verb to “cover” does not necessarily suggest covering all of outer sides of the covered object, and (b) the buffer layer 131 completely covers the top surface of 113 and 120 in a top view.
Regarding claims 4, 7, 8 and 15-18, Chen further discloses that the growth substrate (composite structure of 113 and 120) is a double layer structure, and the double layer structure comprises a first sub-layer (113) and a second sub-layer (120) that are stacked in a direction away from the supporting substrate (111) (claim 4), wherein a thickness of the second sub-layer (120) is less than a depth of each recess (114) (claim 7), further comprising: a source electrode (160) (col. 7, line 40), a drain electrode (170) (col. 7, line 40), and a gate electrode (150 or composite electrode of 140 and 150) (col. 7, line 38) which is disposed between the source electrode and the drain electrode, wherein the source electrode (160), the drain electrode (170), and the gate electrode are all disposed on the heterojunction structure layer (composite layer of 132 and 133, or composite layer of 132-134) (claim 8), a depth of each recess (114) is less than a thickness of the growth substrate (composite structure of 113 and 120), because the plurality of recesses 114 are disposed below and thus separate from the openings OP (claim 15), materials of the supporting substrate (111) and the growth substrate (composite structure of 113 and 120) comprise silicon (col. 3, lines 35-40), because the transitional phrase “comprise” does not preclude presence of other materials (claim 16), a material of the buried layer (112; silicon oxide) comprises at least one of a silicon oxide, a silicon nitride, a silicon nitride oxide, or an aluminum nitride (col. 3, lines 58-59) (claim 17), and a material of the buffer layer (131) comprises a group III nitride material (col. 6, lines 2-4) (claim 18).
Claims 1, 3, 16 and 18 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Brueck et al. (US 10,453,996)
In the below prior art rejection, the claim limitations “growth substrate” and “buffer layer” specify intended uses or fields of use, because (a) the “growth substrate” 301/302 in Fig. 3 of current application is basically a patterned silicon layer of a silicon-on-insulator substrate for growing GaN-based semiconductor materials, and (b) the “buffer layer” 4 in Fig. 3 of current application is a buffer layer and also a channel layer of a high electron mobility transistor, and are treated as non-limiting since it has been held that in device claims, intended use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex Parte Masham, 2 USPQ 2d 1647 (Bd. Pat. App. & Inter. 1987).
Regarding claim 1, Brueck et al. disclose a semiconductor structure (Figs. 1 and 2), comprising: a supporting substrate (not-shown base substrate of silicon-on-insulator substrate 12 in Fig. 1) (col. 8, lines 27-31), because a silicon-on-insulator substate has a three layer stack structure of a base substrate, an insulator layer and a silicon layer, a buried layer (not-shown insulator layer of silicon-on-insulator substrate 12 in Fig. 1), a growth substrate (not-shown silicon layer of silicon-on-insulator substrate 12 in Fig. 1), a buffer layer (16) (col. 9, line 2), and a heterojunction structure layer (composite layer of 18a and 18b in Fig. 1) (col. 10, lines 25-60) that are sequentially stacked, because (a) Applicants do not specifically claim what the heterojunction structure layer is constituted of, (b) the h-GaN region or hexagonal lattice GaN region 18a and the c-GaN region or cubic lattice GaN region 18b are different semiconductor materials having different lattice and band structures, and thus different band gaps due to their different lattice structures and different arrangements of Ga and N atoms, and (c) therefore, the h-GaN region 18a and the c-GaN region 18b form a heterojunction structure, wherein a plurality of recesses (triangular recess in Fig. 1, which is a part of Fig. 2 with plurality of triangular recesses) are disposed on a side, away from the supporting substrate, of the growth substrate (top side of not-shown silicon layer of silicon-on-insulator substrate 12 in Fig. 1), and the buffer layer completely covers a surface (triangular side surface) of the growth substrate, because (a) “a surface” of the growth substrate does not necessarily suggest an entirety of a top surface of the growth substrate, and (b) as shown in Fig. 3 of current application, whose embodiment is directed to Applicant’s elected species, Applicant’s growth substrate, which is a composite structure of the first sub-layer 301 and the second sub-layer 302, has a plurality of surfaces.
Regarding claims 3, 16 and 18, Brueck et al. further disclose that the buffer layer (16) completely fills the plurality of recesses (recesses having a triangular cross section), and a surface (top slanted surface of 16) of a side, away from the growth substrate (base substate of 12), of the buffer layer is a plane (claim 3), materials of the supporting substrate (base substrate of 12) and the growth substrate (silicon layer of 12) comprise silicon (claim 16), and a material of the buffer layer (16) comprises a group III nitride material (col. 8, lines 13-15) (claim 18).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 11,127,848) The teachings of Chen are discussed above.
Regarding claim 5, Chen differs from the claimed invention by not showing that a conductive type of the first sub-layer is an n type, and a conductive type of the second sub-layer is a p type.
Chen further discloses that “In some embodiments, the substrate 111 may be a doped (such as doped with a p-type or an n-type dopant) or an undoped semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, or the like” on lines 45-49 of column 3, and that “In other embodiments, the nucleation layer 120 may be formed by other semiconductor materials, such as doped silicon carbide (e.g. the silicon carbide may be doped with nitrogen or phosphorus to form a n-type semiconductor or doped with aluminum, boron, gallium, or beryllium to form a p-type semiconductor), Group III-V compound semiconductor materials, or the like” on lines 33-40 of column 5.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a conductive type of the first sub-layer 113 can be an n type, and a conductive type of the second sub-layer 120 can be a p type, because (a) when the substrate structure 110 is formed by, for example, SIMOX method, the supporting substrate 111 and the silicon layer portion 113 of the growth substrate would have the same conductivity type, (b) in this case, the conductive type of the first sub-layer 113 can be an n-type as disclosed by Chen, (c) in addition, the conductive type of the second sub-layer 120 can be p-type when aluminum, boron, gallium, or beryllium is introduced into the second sub-layer 120 to form a p-type semiconductor, and (d) since Chen does not specify the conductivity type of the first and second sub-layer, Chen basically discloses four configurations where the first and second sub-layer have a pair of conductivity types of (i) n-type and n-type, respectively, (ii) n-type and p-type, respectively, (iii) p-type and n-type, respectively, and (iv) p-type and p-type, respectively, and the claimed conductivity types correspond to the second configuration.
Regarding claim 9, Chen et al. differ from the claimed invention by not showing that shapes of projections, on a plane in which the growth substrate is located, of the plurality of recesses, are a plurality of strip shapes that are parallel to each other, and an extension direction of each strip shape is parallel to a width direction of the gate electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that shapes of projections, on a plane in which the growth substrate 113/120 is located, of the plurality of recesses114, can be a plurality of strip shapes that are parallel to each other, and an extension direction of each strip shape can be parallel to a width direction of the gate electrode, because (a) a strip or stripe shape of a plan view shape of a recess has been one of the most commonly obtained shapes of recesses depending on the function and utility of the recesses in semiconductor industry such as controlling strain and reducing defects, (b) also, a strip or stripe shape of a plan view shape of a recess has been one of the most commonly obtained shapes of recesses due to its ease and low cost of manufacturing, and (c) the extension direction of the strip shape parallel to a width direction of a gate electrode has been commonly employed to better control charge carriers and an electric field profile created by the gate electrode.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Brueck et al. (US 10,453,996) The teachings of Brueck et al. are discussed above.
Brueck et al. differ from the claimed invention by not showing that a material of the buried layer comprises at least one of a silicon oxide, a silicon nitride, a silicon nitride oxide, or an aluminum nitride.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a material of the buried layer can comprise at least one of a silicon oxide, a silicon nitride, a silicon nitride oxide, or an aluminum nitride, because (a) the buried layer 112 corresponds to an insulator layer of a silicon-on-insulator substrate, and (b) the listed dielectric materials, especially silicon oxide, have been commonly employed as an insulator material of a silicon-on-insulator substrate due to its low cost of manufacturing and well-known dielectric constant.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al. (US 8,030,666)
Norberg et al. (US 10,651,110)
Fang et al. (US 7,639,719)
Liang (US 10,366,883)
Liang (US 9,093,428)
Then et al. (US 2018/0175184)
Kim et al. (US 8,741,706)
Li et al. (US 12,027,602)
Cheng et al. (US 12,446,244)
Fujioka et al. (US 2019/0051538)
Liang (US 10,658,177)
Gallagher et al. (US 10,217,641)
Kaper et al. (US 2010/0295104)
Comeau et al. (US 9,356,045)
Cheng et al. (US 8,487,316)
Wang et al. (CN 116013982)
Cheng et al. (WO 2022/094966)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 April 9, 2026
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