DETAILED ACTION
This Office Action is in response to Amendment filed July 8, 2026.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 3-5, 7-9 and 15-18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor, at the time the application was filed, had possession of the claimed invention.
(1) Regarding claim 1, Applicant originally disclosed in paragraph [0040] of current application that “A plurality of recesses 31 are disposed on a side, away from the supporting substrate 1, of the growth substrate 3, and the buffer layer 4 completely covers a surface of the growth substrate 3 (emphasis added)”, and in paragraph [0049] of current application that “In an embodiment, a material of the buffer layer 4 includes a group III nitride material, the recesses 31 is completely filled with the buffer layer 4, and a surface of a side, away from the growth substrate 3, of the buffer layer 4 is a plane.” However, Applicant did not originally disclose that “the buffer layer completely covers an entire surface of the growth substrate, and the entire surface comprises: top surfaces of regions among the plurality of recesses and inner surfaces of the plurality of recesses (emphasis added)” as recited on lines 6-8, because (a) Applicant only mentioned “a surface” of the growth substrate 3, which is an unspecified “surface” of the growth substrate 3, completely covered by the buffer layer 4 in the original disclosure rather than “an entire surface of the growth substrate” being completely covered by the buffer layer 4, (b) also, Applicant did not originally disclose “top surfaces of regions among the plurality of recesses” and “inner surfaces of the plurality or recesses” since (i) the plurality of recesses are empty spaces, and (ii) therefore, as also discussed below under 35 USC 112(b) rejections, empty spaces do not have top or inner surfaces, (c) it appears that these limitations are derived from Fig. 3 of current application, which is directed to Applicant’s elected species, (d) however, Applicant did not originally disclose the claimed completely coverage with regard to Fig. 3 of current application, (e) furthermore, Fig. 3 of current application lacks any detailed structure of the component layers, (f) for example, Figs. 2A-2D of Nunoue et al. (US 6,316,785) show propagation and creation of dislocations 130 between two GaN layers 102/103, and therefore, there should also be propagation and creation of dislocations between the growth substrate 301/302 and the buffer layer 4 in Fig. 3 of current application, which is directed to Applicant’ elected species, and (g) in this case, “the buffer layer” cannot completely cover “an entire surface of the growth substrate, and the entire surface comprises: top surfaces of regions among the plurality of recesses and inner surfaces of the plurality of recesses” as recited on lines 6-8 in the presence of dislocations since the areas of the buffer layer 4 in Fig. 3 of current application where the dislocations propagate or the dislocations are created do not completely cover the underlying growth substrate 301/302 due to the presence of empty spaces created by the dislocations.
(2) Further regarding claim 1, Applicant did not originally disclose that “the buffer layer completely covers an entire surface of the growth substrate, and the entire surface comprises: top surfaces of regions among the plurality of recesses and inner surfaces of the plurality of recesses (emphases added)” as recited on lines 6-8, because (a) the transitional phrase “comprises” does not preclude other surfaces that can be a part or parts of the claimed “entire surface”, i.e. Applicant does not claim that “the entire surface consists of”, (b) furthermore, without Applicant’s specifically defining what the “regions among the plurality of recesses” refer to, the top surfaces of the first sub-layer 301 should also be included in the “regions among the plurality of recesses” since the first sub-layer 301 is different from the second sub-layer 302, and (c) however, the entirety of the top surfaces of the first sub-layer 301 are not completely covered by the buffer layer 4 in Fig. 3 of current application.
Claims 3-5, 7-9 and 15-18 depend on claim 1, and therefore, claims 3-5, 7-9 and 15-18 also fail to comply with the written description requirement.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-5, 7-9 and 15-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(1) Regarding claim 1, it is not clear what the limitation “regions among the plurality of recesses” recited on line 7 suggests, because (a) while the limitation “regions among the plurality of recesses” per se may be broadly interpreted, Applicant does not claim “regions among the plurality of recesses” per se, but rather claim “the entire surface comprises: top surfaces of regions among the plurality of recesses” on lines 6-7, (b) therefore, depending on how the limitation “regions among the plurality of recesses” is interpreted, the claimed buffer layer would have distinct structure and/or sizes, (c) for example, along the lines discussed above under 35 USC 112(a) rejections, it is not clear whether the first sub-layer 301 and the second sub-layer 302 are different regions or a single region, and (d) furthermore, the limitation “regions among the plurality of recesses” does not necessarily suggest all the regions among the plurality of recesses, and therefore, the claimed “entire surface” comprising “top surfaces of regions among the plurality of recesses” recited on lines 6-7 does not necessarily suggest the entire surface that Applicant may have intended to claim.
(2) Also regarding claim 1, it is not clear how “regions among the plurality of recesses” can have “top surfaces” and “the plurality of recesses” recited on lines 7-8, because (a) recesses are basically empty spaces that do not have any tangible structural features, (b) therefore, technically the plurality of recesses do not have any top surfaces and inner surfaces, and for example, it is not clear what the inner spaces of the plurality of recesses refer to since Applicant claims inner spaces of empty spaces, and (c) in this case, the buffer layer cannot completely cover the entire surface of the growth substrate comprising “top surfaces of regions among the plurality of recesses and inner surfaces of the plurality of recesses”.
Claims 3-5, 7-9 and 15-18 depend on claim 1, and therefore, claims 3-5, 7-9 and 15-18 are also indefinite.
(3) Regarding claim 3, it is not clear what the limitation “the buffer layer completely fills the plurality of recesses” recited on lines 1-2 refers to, because (a) as recited in claims 16 and 18, the buffer layer comprises a group III nitride material, and the growth substrate comprises silicon, (b) however, as Fig. 2-12, 14, 15, 18 and 24 of Brueck et al. (US 10,453,996) show, actual GaN-based semiconductor materials deposited on recessed Si-based substrates would not completely and directly cover the underlying, exposed surfaces of the Si-based substrates due to their different crystalline structures and different lattice constants as well as different atomic sizes of the constituent elements and surface roughness of the underlying Si-based substrates with steps and terraces, (c) it appears that the claim limitation cited above is derived from the feature illustrated in Fig. 3 of current application, but Fig. 3 of current application is a mere schematic illustration that does not represent an actual structure down to the atomic levels and does not show any detailed structures of the buffer layer and the growth substrate, while Brueck et al. show actual structures of GaN-based semiconductor materials deposited on recessed Si-based substrates, (d) the group III nitride material constituting the buffer layer is a solid material, and therefore, once deposited, the group III nitride material cannot be modified to conform to the surface profiles of the underlying growth substrate, (e) therefore, it is not clear how the limitation “the buffer layer completely fills the plurality of recesses” is defined unambiguously, and (f) it is not clear whether all of the bottommost atoms constituting the buffer layer are bonded to all of the exposed atoms constituting the growth substrate, which is not actually and physically possible since the atomic size of the silicon atoms are different from the atomic sizes of group III element atoms and nitrogen atoms constituting the buffer layer, and it is not clear whether there should not be a void or cavity larger than a certain, unspecified size to be referred to be a configuration where “the buffer layer completely fills the plurality of recesses”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 4, 7, 15, 17 and 18 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Hata et al. (US 2005/0263778)
In the below prior art rejection, the claim limitations “growth substrate” and “buffer layer” specify intended uses or fields of use, because (a) the “growth substrate” 301/302 in Fig. 3 of current application is basically a patterned silicon layer of a silicon-on-insulator substrate for growing GaN-based semiconductor materials, and (b) the “buffer layer” 4 in Fig. 3 of current application is a buffer layer and also a channel layer of a high electron mobility transistor, and are treated as non-limiting since it has been held that in device claims, intended use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex Parte Masham, 2 USPQ 2d 1647 (Bd. Pat. App. & Inter. 1987).
Regarding claims 1, 3, 4, 7, 15, 17 and 18, Hata et al. disclose a semiconductor structure (Fig. 21), comprising: a supporting substrate (41) ([0084]), a buried layer (42) ([0085]), a growth substrate (43 or composite structure of 43 and 44) ([0085]-[0086]), because (a) the undoped GaN layer 45 is grown on the undoped GaN underlayer 43 and the SiO2 mask layer 44 just like Applicant’s growth substrate 301/302 in Fig. 3 of current application, and (b) the limitation “growth substrate” is directed to an intended use as discussed above, a buffer layer (45 in Fig. 21) ([0089]), because the limitation “buffer layer” is also directed to an intended use as discussed above, and a heterojunction structure layer (all or some of composite layer of 5-13) ([0060]-[0061]) that are sequentially stacked, wherein a plurality of recesses (Fig. 16) are disposed on a side, away from the supporting substrate, of the growth substrate, and the buffer layer completely covers a surface of the growth substrate (43 or composite structure of 43 and 44), because the buffer layer 45 completely covers the a surface of 43 and 44 in the drawing of Fig. 21 of Hata et al.; and the buffer layer completely covers an entire surface of the growth substrate, and the entire surface comprises: top surfaces of regions among the plurality of the recesses and inner surfaces of the plurality of recesses (claim 1), wherein the buffer layer (45) completely fills the plurality of recesses, and a surface of a side, away from the growth substrate, of the buffer layer is a plane (claim 3), the growth substrate (composite structure of 43 and 44) is a double layer structure, and the double layer structure comprises a first sub-layer (43) and a second sub-layer (44) that are stacked in a direction away from the supporting substrate (41) (claim 4), wherein a thickness of the second sub-layer (44) is less than a depth of each recess (claim 7), a depth of each recess is less than a thickness of the growth substrate (composite structure of 43 and 44), because the underlayer 43 is only partially removed (claim 15), a material of the buried layer (42) comprises at least one of a silicon oxide, a silicon nitride, a silicon nitride oxide, or an aluminum nitride, because (a) Hata et al. further disclose that the low-temperature buffer layer 42 is formed of AlGaN ([0085]), and (b) AlGaN is a solid solution of AlN and GaN, and thus comprises aluminum nitride (claim 17), and a material of the buffer layer (45) comprises a group III nitride material ([0088]) (claim 18).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Hata et al. (US 2005/0263778) The teachings of Hata et al. are discussed above.
Regarding claim 8, Hata et al. differ from the claimed invention by not further comprising: a source electrode, a drain electrode, and a gate electrode which is disposed between the source electrode and the drain electrode, wherein the source electrode, the drain electrode, and the gate electrode are all disposed on the heterojunction structure layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the semiconductor structure disclosed by Hata et al. can further comprise a source electrode, a drain electrode, and a gate electrode which is disposed between the source electrode and the drain electrode, wherein the source electrode, the drain electrode, and the gate electrode are all disposed on the heterojunction structure layer, because (a) Hata et al. further disclose in paragraph [0117] that “While the nitride-based semiconductors are employed for preparing semiconductor laser devices in the aforementioned first to fourth embodiments, the present invention is not restricted to this but also applicable to another device such as a light emitting diode device or a transistor employing a nitride-based semiconductor (emphasis added)”, and (b) the claimed configuration of the source, drain and gate electrode with respect to the heterojunction structure layer have been a commonly employed configuration with the heterojunction structure layer being a GaN-based channel layer and an AlGaN-based electron supply layer or barrier layer instead of the light-emitting layer heterojunction structure layer shown in Fig. 21 of Hata et al.
Regarding claim 9, Hata et al. further disclose that shapes of projections, on a plane in which the growth substrate (composite structure of 43 and 44) is located, of the plurality of recesses, are a plurality of strip shapes that are parallel to each other, see Fig. 21, and an extension direction of each strip shape is parallel to a with direction of the gate electrode, which would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention when the source electrode, drain electrode and gate electrode recited in claim 8 are formed as recited in claim 8.
Regarding claim 16, Hata et al. further disclose for the semiconductor structure according to claim 1 that material of the growth substrate (composite structure of 43 and 44) comprises silicon ([0086]), because (a) the transitional phrase “comprise” does not preclude presence of other materials, and (b) the SiO2 mask 44 comprises silicon.
Hata et al. differ from the claimed invention by not showing that material of the supporting substrate comprises silicon.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that material of the supporting substrate 41 can comprise silicon, because (a) a sapphire substrate and a substrate comprising silicon such as a silicon substrate and a silicon carbide substrate have been commonly and interchangeably employed in manufacturing GaN-based semiconductor devices due to their lattice structure being similar to GaN-based semiconductor materials, and (b) in addition, a silicon substrate and a silicon carbide substrate have been commonly employed due to their low cost.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments traversing the 35 USC 112(b) rejection of claim 3 in the REMARKS are not persuasive, because (a) Applicant makes allegations without providing any substantiating evidence, not to mention the allegations not being based on the original disclosure, (b) it appears that Applicant argues that, even if there is a gap between the buffer layer and the underlying structure, the buffer layer “completely fills” the plurality of recesses, and if this is the case, it is not clear how big the gap can be, i.e. is it 1 nm gap or 10 nm gap?, for example, (c) furthermore, Applicant’s allegations citing the standard industrial inspection techniques such as SEM are not persuasive since the resolution of the standard industrial inspection techniques such as SEM would vary over time with the advancement of the science and technology, (d) therefore, if arguendo Applicant’s arguments in the REMARKS are correct, the definition of the phrase “completely fills” would change over time, rendering claim 1 further indefinite if Applicant’s arguments are correct, and (e) in this case, it is not clear what the definition of the phrase “completely fills” is at the time current application was filed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tsuda et al. (US 6,620,238)
Sharma et al. (US 8,227,820)
Sun et al. (US 10,211,048)
Lin et al. (US 9,711,683)
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 August 11, 2026
Prosecution Insights