Prosecution Insights
Last updated: July 17, 2026
Application No. 18/347,583

ELECTRONIC DEVICE

Final Rejection §102§103
Filed
Jul 06, 2023
Priority
Aug 11, 2022 — CN 202210963465.1
Examiner
DEGRASSE, IAN ISAAC
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Carux Technology Pte. Ltd.
OA Round
2 (Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
5m
Est. Remaining
74%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
17 granted / 22 resolved
+9.3% vs TC avg
Minimal -4% lift
Without
With
+-3.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
42 currently pending
Career history
74
Total Applications
across all art units

Statute-Specific Performance

§103
75.5%
+35.5% vs TC avg
§102
20.5%
-19.5% vs TC avg
§112
4.1%
-35.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 22 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-13, 15-16 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0221948 A1 to Xu et al. (hereinafter “Xu” – previously cited reference). Regarding claim 1, Xu discloses electronic device comprising: a first substrate (electronic device 100 having substrate 110; Fig. 1A; paragraph [0036]); a circuit assembly disposed on the first substrate (flexible PCB 130 disposed on substrate 110; Fig. 1A; paragraph [0036]); a second substrate disposed on the circuit assembly (cover 180 disposed over PCB 130; Fig. 1A); a first adhesive layer disposed between the circuit assembly and the first substrate, the first adhesive layer having a first outer profile (conductive glue C and adhesive colloid 160 disposed between substrate 110 and PCB 130, where glue and colloid have a first outer profile; Fig. 1A; paragraphs [0036], [0038], [0041]); and a second adhesive layer disposed between the circuit assembly and the second substrate, the second adhesive layer having a second outer profile (adhesive colloid 150 disposed between PCB 130 and substrate 110, where colloid has a second outer profile; Fig. 1A; paragraphs [0036], [0038], [0041]), wherein the first outer profile and the second outer profile correspond to a same side of the electronic device, and at least a portion of the first outer profile and at least a portion of the second outer profile are non-overlapped (outer profiles correspond to same side of device 100 and are non-overlapping; Fig. 1A); in a normal direction of the electronic device, at least a portion of the first adhesive layer and at least a portion of the second adhesive layer are sandwiched between the first substrate and the second substrate (conductive glue C and adhesive colloid disposed between substrate 110 and cover 180 in a vertical direction; Fig. 1A), and at least another portion of the first adhesive layer and at least another portion of the second adhesive layer extend beyond the first substrate and the second substrate (part of adhesive colloid 150 disposed outside of substrate 110 and part of adhesive colloid 160 disposed outside of cover 180; Fig. 1A). Regarding claim 2, Xu discloses the electronic device according to claim 1, wherein the first substrate has a first profile, the second substrate has a second profile, the first profile and the second profile correspond to a same side of the electronic device (substrate 110 and cover 180 have first and second profiles corresponding to same side of device 100; Fig. 1A), and a first distance between the first profile and the first outer profile is different from a second distance between the second profile and the second outer profile (distance between first profile and first outer profile is different than distance between second profile and second outer profile; Fig. 1A). Regarding claim 3, Xu discloses the electronic device according to claim 2, wherein a difference between the first distance and the second distance is greater than 0 micrometer and less than 10 millimeters (first distance may be zero and second distance may be 50 microns, which provides a difference of 50 microns; Fig. 1A; paragraph [0040]). Regarding claim 4, Xu discloses the electronic device according to claim 3, wherein the difference between the first distance and the second distance is greater than 0 micrometer and less than 100 micrometers (first distance may be zero and second distance may be 50 microns, which provides a difference of 50 microns; Fig. 1A; paragraph [0040]). Regarding claim 5, Xu discloses the electronic device according to claim 1, wherein the at least a portion of the first outer profile is outside the first substrate (part of the first outer profile is outside of substrate 110; Fig. 1A). Regarding claim 6, Xu discloses the electronic device according to claim 1, wherein the at least a portion of the first outer profile is overlapped with the first substrate in a normal direction of the electronic device (part of the first outer profile overlaps with substrate 110 in vertical direction normal to device 100; Fig. 1A). Regarding claim 7, Xu discloses the electronic device according to claim 1, wherein the at least another portion of the first adhesive layer and the at least another portion of the second adhesive layer are disposed at a same side of the electronic device (parts of first and second outer profiles on same side of device 100; Fig. 1A), and a first thickness of the at least another portion of the first adhesive layer is different from a second thickness of the at least another portion of the second adhesive layer (thicknesses of parts of first and second outer profiles are different relative one another; Fig. 1A). Regarding claim 8, Xu discloses the electronic device according to claim 7, wherein a difference between the first thickness and the second thickness is from 0.1 millimeter to 10 millimeters (thickness of part of first outer profile may be no larger than 0.4 mm and thickness of part of second outer profile may be between 0.5 and 1.5 mm; paragraphs [0039], [0057]). Regarding claim 9, Xu discloses the electronic device according to claim 7, wherein a difference between the first thickness and the second thickness is from 0.1 micrometer to 100 micrometers (thickness of part of first outer profile may be no larger than 100 microns and thickness of part of second outer profile may be between 20 and 60 microns; paragraphs [0049], [0055]). Regarding claim 10, Xu discloses the electronic device according to claim 7, wherein the at least another portion of the first adhesive layer extends to a side surface of the first substrate and has a first extended distance, the at least another portion of the second adhesive layer extends to a side surface of the second substrate and has a second extended distance, and the first extended distance of the first adhesive layer is different from the second extended distance of the second adhesive layer (parts of first and second outer profiles extend in a direction to the side surfaces of each of substrate 110 and cover 180, respectively, where distance extended in the direction differs between the first and second outer profiles; Fig. 1A). Regarding claim 11, Xu discloses the electronic device according to claim 10, wherein a difference between the first extended distance and the second extended distance is from 100 micrometers to 10 millimeters (extended distance of part of first outer profile may be no larger than 0.4 mm and extended distance of part of second outer profile may be between 70 and 110 microns; paragraphs [0049], [0057]). Regarding claim 12, as best understood, Xu discloses the electronic device according to claim 10, wherein a difference between the first extended distance and the second extended distance is from 0.1 micrometer to 100 micrometers (extended distance of part of first outer profile may be no larger than 100 microns and extended distance of part of second outer profile may be between 70 and 110 microns; paragraphs [0049], [0055]). Regarding claim 13, Xu discloses the electronic device according to claim 1, further comprising: a protective element disposed on at least one of the first outer profile and the second outer profile (transparent glue layer 170 disposed upon second outer profile; Fig. 1A; paragraph [0053]). Regarding claim 15, Xu discloses the electronic device according to claim 1, wherein at least a portion of the circuit assembly is outside the first substrate (part of PCB 130 outside of substrate 110; Fig. 1A). Regarding claim 16, Xu discloses the electronic device according to claim 1, comprising a transparent display device, a transparency adjustment device, an antenna device, a sensing device, or a heating device (device 100 may comprise a touch screen; paragraph [0041]). Regarding claim 19, Xu discloses the electronic device according to claim 1, wherein a shape of the first outer profile is different from a shape of the second outer profile (first and second outer profile shapes differ; Fig. 1A). Regarding claim 20, Xu discloses the electronic device according to claim 1, wherein the first outer profile is within the first substrate (part of first outer profile of conductive glue C and adhesive colloid 160 is within horizontal extent of substrate 110; Fig. 1A). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Xu in further view of US 2021/0392760 A1 to Huang et al. (hereinafter “Huang”). Regarding claim 14, Xu discloses the electronic device according to claim 1. Xu fails to disclose wherein the circuit assembly comprises a first circuit substrate and a second circuit substrate, the first circuit substrate is located between the first adhesive layer and the second adhesive layer, and the second circuit substrate is electrically connected to the first circuit substrate. However, Huang discloses wherein the circuit assembly comprises a first circuit substrate and a second circuit substrate, the first circuit substrate is located between the first adhesive layer and the second adhesive layer, and the second circuit substrate is electrically connected to the first circuit substrate (display device 1 circuit comprises first substrate 110 disposed between adhesives 14, 16 and electrically connected to circuit board 150 via conductive adhesive 16; Fig. 1; paragraph [0028]). Xu and Huang are both considered to be analogous to the claimed invention because they are in the same field of electronic devices utilizing multiple substrates and adhesive layers. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Xu to incorporate the teaching of Huang in order to potentially provide improved space efficiency and miniaturization, reduced interconnects and enhanced reliability, lower weight and simplified assembly, and better signal integrity and performance. Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Xu in further view of US 2021/0078388 A1 to Astete et al. (hereinafter “Astete”). Regarding claim 17, Xu discloses the electronic device according to claim 1. Xu fails to disclose wherein the first substrate has a first refractive index n1, the first adhesive layer has a second refractive index n2, and the first refractive index n1 and the second refractive index n2 satisfy: PNG media_image1.png 100 301 media_image1.png Greyscale . However, Astete discloses wherein the first substrate has a first refractive index n1, the first adhesive layer has a second refractive index n2, and the first refractive index n1 and the second refractive index n2 satisfy: PNG media_image1.png 100 301 media_image1.png Greyscale (compensation layer 12 and laminating resin layer may have matched refractive indexes, which provides for a numerator of zero; Fig. 2; paragraphs [0058], [0061]-[0062]). Xu and Astete are both considered to be analogous to the claimed invention because they are in the same field of electronic devices utilizing multiple substrates and adhesive layers. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Xu to incorporate the teaching of Astete in order to potentially provide minimized internal reflections and light loss, reduced optical distortion and interference, enhanced contrast, clarity, and color accuracy, and improved durability and environmental resistance. Regarding claim 18, Xu in view of Astete discloses the electronic device according to claim 17. Xu fails to disclose wherein the circuit assembly comprises a first circuit substrate, the first circuit substrate is disposed between the first adhesive layer and the second adhesive layer, the first circuit substrate has a third refractive index n3, and the second refractive index n2 and the third refractive index n3 satisfy: PNG media_image2.png 97 300 media_image2.png Greyscale . However, Astete discloses wherein the circuit assembly comprises a first circuit substrate, the first circuit substrate is disposed between the first adhesive layer and the second adhesive layer, the first circuit substrate has a third refractive index n3, and the second refractive index n2 and the third refractive index n3 satisfy: PNG media_image2.png 97 300 media_image2.png Greyscale (substrate of circuit insert 44 and laminating resin layer may have matched refractive indexes, which provides for a numerator of zero, where substrate is disposed between laminating resin layer and adhesive plastic interlayers 4; Fig. 2; paragraphs [0058], [0061]-[0062]). Xu and Astete are both considered to be analogous to the claimed invention because they are in the same field of electronic devices utilizing multiple substrates and adhesive layers. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Xu to incorporate the teaching of Astete in order to potentially provide minimized internal reflections and light loss, reduced optical distortion and interference, enhanced contrast, clarity, and color accuracy, and improved durability and environmental resistance. Response to Arguments Applicant's arguments filed March 23, 2026 have been fully considered. Applicant presented substantive amendments to claim 1 and corresponding arguments. Examiner confirms that the 35 USC 112(b) rejection of 12 has been overcome. Further, Applicant asserts that Xu does not disclose amended claim 1, but Applicant does not consider the interpretation utilized by Examiner, where these amendments are satisfied by the conductive glue C and adhesive colloid being disposed between substrate 110 and cover 180 in a vertical direction and by the part of adhesive colloid 150 being disposed outside of substrate 110 and part of adhesive colloid 160 being disposed outside of cover 180 as collectively shown in Fig. 1A. Therefore, Xu discloses amended claim 1. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /IAN DEGRASSE/Examiner, Art Unit 2818 /JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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Prosecution Timeline

Jul 06, 2023
Application Filed
Dec 30, 2025
Non-Final Rejection mailed — §102, §103
Mar 23, 2026
Response Filed
Jun 03, 2026
Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
74%
With Interview (-3.6%)
3y 6m (~5m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 22 resolved cases by this examiner. Grant probability derived from career allowance rate.

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