DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-22, 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu(USPGPUB DOCUMENT: 2023/0402438, hereinafter Liu) in view of Zhang (USPGPUB DOCUMENT: 2022/0262751, hereinafter Zhang) and Lee (USPGPUB DOCUMENT: 2018/0358288, hereinafter Lee).
Re claim 1 Liu discloses a chip(104) package structure, comprising: a heat dissipation base(110)(since 110 may be a silicon substrate, this may be interpreted as a heat dissipation base)[0050]; a second redistribution layer(108) disposed on the heat dissipation base(110) and thermally coupled (by way of 116) to the heat dissipation base(110), and the second redistribution layer(108) is located between the first layer(124) and the heat dissipation base(110); a chip(102/104) disposed between the second redistribution layer(108) and the first layer(124), a plurality of chips(102/104) disposed between the second redistribution layer(108) and the first layer(124) and having different thicknesses;
wherein each of the chips(102/104) has an active surface(518/520) facing the first layer(124) and an inactive surface(518/520) facing the second redistribution layer(108), and the active surface(518/520) of the chips(102/104) are electrically connected to the first redistribution layer(76/78); wherein the inactive surfaces(surface inactive to 104/102) of the chips(102/104) are thermally coupled to the second redistribution layer(108);
a plurality of metal stacks(112)[0048] disposed between the second redistribution layer(108) and the inactive surfaces(surface inactive to 104/102) of the chips(102/104), wherein the inactive surfaces(surface inactive to 104/102) of the chips(102/104) are thermally coupled to the second redistribution layer(108) via the metal stacks(112)[0048], and the metal stacks(112)[0048] have different thicknesses;
Liu does not disclose a first redistribution layer(210/102); and the second redistribution layer(108) is located between the first redistribution layer(210/102) and the heat dissipation base(110); a chip(102/104) disposed between the second redistribution layer(108) and the first redistribution layer(210/102), a plurality of chips(102/104) disposed between the second redistribution layer(108) and the first redistribution layer(210/102) and having different thicknesses;
wherein each of the chips(102/104) has an active surface(518/520) facing the first redistribution layer(210/102) and an inactive surface(518/520) facing the second redistribution layer(108), and the active surface(518/520) of the chips(102/104) are electrically connected to the first redistribution layer(76/78); wherein the inactive surfaces(surface inactive to 104/102) of the chips(102/104) are thermally coupled to the second redistribution layer(108);
and the metal stacks(112)[0048] have different thicknesses;
a plurality of conductive structures(208/legs of 102) disposed between the second redistribution layer(108) and the first redistribution layer(210/102) and electrically connected to the second redistribution layer(108) and the first redistribution layer(210/102),
a plurality of conductive structures(208/legs of 102) disposed between the second redistribution layer(108) and the first layer(124) and electrically connected to the second redistribution layer(108) and the first layer(124), wherein each of the conductive structures(208/legs of 102) comprises a metal inner core(lid portion of120/208 layer) and a metal outer layer(leg portions of120/208 layer) covering the metal inner core(lid portion of120/208 layer), and the metal inner core(lid portion of120/208 layer) is partially exposed on the metal outer layer(leg portions of120/208 layer) to be in contact(by way of left/right 112) with the second redistribution layer(108);
Zhang disclose in Fig 10A, rotated 180 degrees, a first redistribution layer(15/14 of Zhang); a plurality of chips(33/34/32 of Zhang) having different thicknesses;
and the metal stacks(112)[0048] have different thicknesses[0093 of Zhang];
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Zhang to the teachings of Liu in order to achieve better performance, greater miniaturization, and higher reliability [0002, Zhang]. In doing so, and the second redistribution layer(108) is located between the first redistribution layer(15/14 of Zhang) and the heat dissipation base(110); a chip(102/104) disposed between the second redistribution layer(108) and the first redistribution layer(15/14 of Zhang), a plurality of chips(33/34/32 of Zhang) disposed between the second redistribution layer(108) and the first redistribution layer(15/14 of Zhang) and having different thicknesses;
wherein each of the chips(102/104) has an active surface(518/520) facing the first redistribution layer(15/14 of Zhang) and an inactive surface(518/520) facing the second redistribution layer(108), and the active surface(518/520) of the chips(102/104) are electrically connected to the first redistribution layer(15/14 of Zhang); wherein the inactive surfaces(surface inactive to 104/102) of the chips(102/104) are thermally coupled to the second redistribution layer(108);
and the metal stacks(112)[0048] have different thicknesses[0093 of Zhang];
a plurality of conductive structures(208/legs of 102) disposed between the second redistribution layer(108) and the first redistribution layer(15/14 of Zhang) and electrically connected to the second redistribution layer(108) and the first redistribution layer(15/14 of Zhang),
Liu and Zhang does not disclose a plurality of conductive structures(208/legs of 102) disposed between the second redistribution layer(108) and the first layer(124) and electrically connected to the second redistribution layer(108) and the first layer(124), wherein each of the conductive structures(208/legs of 102) comprises a metal inner core(lid portion of120/208 layer) and a metal outer layer(leg portions of120/208 layer) covering the metal inner core(lid portion of120/208 layer), and the metal inner core(lid portion of120/208 layer) is partially exposed on the metal outer layer(leg portions of120/208 layer) to be in contact(by way of left/right 112) with the second redistribution layer(108);
Lee disclose a plurality of conductive structures(120 of Lee), wherein each of the conductive structures(120 of Lee) comprises a metal inner core and a metal outer layer covering the metal inner core, and the metal inner core is partially exposed on the metal outer layer to be in contact with the second redistribution layer(RDL of Lee);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lee to the teachings of Liu in order to achieve dissipation heat of a semiconductor chip and suppressing warpage of the semiconductor chip [0001, Lee]. In doing so, a plurality of conductive structures(120 of Lee) disposed between the second redistribution layer(108) and the first redistribution layer(15/14 of Zhang) and electrically connected to the second redistribution layer(108) and the first redistribution layer
Re claim 2 Liu and Zhang disclose the chip(104) package structure of claim 1, wherein each of the metal stacks(112)[0048](148/142 of Zhang) comprises a first metal layer and a second metal layer, the first metal layer is located between the second redistribution layer(108) and the second metal layer, and the second metal layer is located between the first metal layer and the inactive surface(518/520) of the corresponding chip(104).
Re claim 3 Liu and Zhang disclose the chip(104) package structure of claim 2, wherein the first metal layers of the metal stacks(112)[0048](148/142 of Zhang) have different thicknesses.
Re claim 4 Liu and Zhang disclose the chip(104) package structure of claim 3, wherein a thickness of the first metal layer of one of the metal stacks(112)[0048](148/142 of Zhang) connected to one of the thicker chips(102/104) is less than a thickness of the first metal layer of another metal stack connected to another thinner chip(104).
Re claim 5 Liu and Zhang disclose the chip(104) package structure of claim 3, wherein a total thickness of one of the chips(102/104) and one of the metal stacks(112)[0048](148/142 of Zhang) connected to each other is equal to a total thickness of another chip(104) and another metal stack connected to each other.
Re claim 6 Liu and Zhang disclose the chip(104) package structure of claim 2, wherein the second metal layers of the metal stacks(112)[0048](148/142 of Zhang) have a same thickness.
Re claim 7 Liu and Zhang disclose the chip(104) package structure of claim 2, wherein a material of the first metal layer of each of the metal stacks(112)[0048](148/142 of Zhang) comprises copper, and a material of the second metal layer comprises tin.
Re claim 8 Liu and Zhang disclose the chip(104) package structure of claim 1, wherein the metal outer layer(leg portions of120/208 layer) of each of the conductive structures(208/legs of 102) has a first contact surface in contact with the secondredistribution layer, the metal inner core(lid portion of120/208 layer) has a second contact surface exposed to the first contact surface, and the second contact surface is in contact with the second redistribution layer(108).
Re claim 9 Liu and Zhang disclose the chip(104) package structure of claim 8, wherein the first contact surface of the metal outer layer(leg portions of120/208 layer) of each of the conductive structures(208/legs of 102) and the second contact surface of the metal inner core(lid portion of120/208 layer) are coplanar.
Re claim 10 Liu and Zhang disclose the chip(104) package structure of claim 8, wherein the first contact surface of the metal outer layer(leg portions of120/208 layer) of each of the conductive structures(208/legs of 102) surrounds the second contact surface of the metal inner core(lid portion of120/208 layer).
Re claim 11 Liu and Zhang disclose the chip(104) package structure of claim 1, wherein the metal outer layer(leg portions of120/208 layer) of each of the conductive structures(208/legs of 102) is in contact with the first redistribution layer(210/102), and the metal inner core(lid portion of120/208 layer) and the first redistribution layer(210/102) are separated by the metal outer layer(leg portions of120/208 layer).
Re claim 12 Liu and Zhang disclose the chip(104) package structure of claim 1, wherein each of the conductive structures(208/legs of 102) is a conductive ball or a conductive pillar(see Fig 2 of Liu).
Re claim 13 Liu and Zhang disclose the chip(104) package structure of claim 1, wherein a material of the metal inner core(lid portion of120/208 layer) of each of the conductive structures(208/legs of 102) is copper, and a material of the metal outer layer(leg portions of120/208 layer) is tin.
Re claim 14 Liu and Zhang disclose the chip(104) package structure of claim 1, wherein a material of the heat dissipation base(110) comprises copper or silicon.
Re claim 15 Liu and Zhang disclose the chip(104) package structure of claim 1, further comprising: a plurality of underfill layers respectively disposed between the active surface(518/520) of the chips(102/104) and the first redistribution layer(210/102).
Re claim 16 Liu and Zhang disclose the chip(104) package structure of claim 15, wherein each of the chips(102/104)also has a side surface connected to the active surface(518/520), and the underfill layer further covers the side surface of the chip(104) and covers the metal stack.
Re claim 17 Liu and Zhang disclose the chip(104) package structure of claim 1, further comprising a third redistribution layer[0054,0055 of Zhang], wherein the third redistribution layer[0054,0055 of Zhang] is disposed on the first redistribution layer(210/102), and the first redistribution layer(210/102) is located between the encapsulant and the third redistribution layer[0054,0055 of Zhang].
Re claim 18 Liu and Zhang disclose the chip(104) package structure of claim 17, wherein the third redistribution layer[0054,0055 of Zhang] comprises a molding layer covering the first redistribution layer(210/102), at least two circuits[0031 of Zhang] disposed on the molding layer, and at least two conductive vias penetrating through the molding layer, and the two circuits[0031 of Zhang] are respectively electrically connected to the first redistribution layer(210/102) via the two conductive vias.
Re claim 19 Liu and Zhang disclose the chip(104) package structure of claim 17, wherein the third redistribution layer[0054,0055 of Zhang] comprises a first molding layer covering the first redistribution layer(210/102), a second molding layer disposed above the first molding layer, a dielectric layer[0055 of Zhang] and a first circuit disposed between the first molding layer and the second molding layer, a second circuit and a third circuit disposed on the second molding layer, a first conductive via, a second conductive via, and a third conductive via, the first conductive via penetrates through the first molding layer, and the first circuit is electrically connected to the first redistribution layer(210/102) via the first conductive via, the second conductive via and the third conductive via penetrate through the second molding layer, the dielectric layer[0055 of Zhang], and the first molding layer, and the second circuit and the third circuit are electrically connected to the first redistribution layer(210/102) via the second conductive via and the third conductive via respectively.
Re claim 20 Liu and Zhang disclose the chip(104) package structure of claim 17, wherein the third redistribution layer[0054,0055 of Zhang] comprises a molding layer disposed above the first redistribution layer(210/102), at least two circuits[0031 of Zhang] disposed at a side of the molding layer, at least two conductive vias penetrating through the molding layer, and at least two conductive pads and at least two conductive balls disposed at another side of the molding layer, and the two conductive balls are located between the first redistribution layer(210/102) and the two conductive pads, and each of the circuits[0031 of Zhang] is electrically connected to the first redistribution layer(210/102) via one of the conductive vias, one of the conductive pads, and one of the conductive balls.
Re claim 21 Liu and Zhang disclose the chip(104) package structure of claim 1, wherein the heat dissipation base(110) comprises a plurality of heat dissipation portions and a plurality of electrical transmission portions, the heat dissipation portions are respectively located opposite to the chips(102/104) and thermally coupled to the second redistribution layer(108), and the electrical transmission portions are located in a periphery of the heat dissipation portions, wherein the electrical transmission portions are respectively located opposite to the conductive structures(208/legs of 102) and electrically connected to the second redistribution layer(108).
Re claim 22 Liu and Zhang disclose the chip(104) package structure of claim 1, wherein each of the metal stacks(112)[0048](148/142 of Zhang) comprises a metal layer and a sintered material layer[0046 of Zhang], wherein the metal layer is located between the second redistribution layer(108) and the sintered material layer[0046 of Zhang], and the sintered material layer[0046 of Zhang] is located between the metal layer and the inactive surface(518/520) of the corresponding chip(104).
Re claim 36 Liu discloses in Fig 2, rotated 180 degrees, a chip(104) package structure, comprising: a heat dissipation base(110); a first layer(210/102); a second redistribution layer(108) disposed on the heat dissipation base(110) and thermally coupled to the heat dissipation base(110), and the second redistribution layer(108) is located between the first layer(210/102) and the heat dissipation base(110); a chip(104) disposed between the second redistribution layer(108) and the first layer(210/102), wherein the chip(104) has an active surface(518/520) facing the first layer(210/102) and an inactive surface (surface inactive to 216) facing the second redistribution layer(108), and the active surface(518/520) is electrically connected to the first layer;
a metal stack disposed between the second redistribution layer(108) and the inactive surface(surface inactive to 216), and the inactive surface(surface inactive to 216) is thermally coupled to the second redistribution layer(108) via the metal stack;
Liu does not disclose
a first redistribution layer(210/102); and the second redistribution layer(108) is located between the first redistribution layer(210/102) and the heat dissipation base(110); a chip(104) disposed between the second redistribution layer(108) and the first redistribution layer(210/102), wherein the chip(104) has an active surface(518/520) facing the first redistribution layer(210/102), and the active surface(518/520) is electrically connected to the first redistribution layer(76/78);
a plurality of conductive structures(208/legs of 102) disposed between the second redistribution layer(108) and the first redistribution layer(210/102) and electrically connected to the second redistribution layer(108) and the first redistribution layer(210/102), wherein each of the conductive structures(208/legs of 102) comprises a metal inner core(lid portion of120/208 layer) and a metal outer layer(leg portions of120/208 layer) covering the metal inner core,
the metal inner core and the metal outer layer(leg portions of120/208 layer) are partially removed so that the metal inner core is partially exposed on the metal outer layer(leg portions of120/208 layer) to be in contact with the second redistribution layer(108); and an encapsulant filled between the second redistribution layer(108) and the first redistribution layer(210/102).
Zhang disclose in Fig 10A, rotated 180 degrees, a first redistribution layer(15/14 of Zhang); and the second redistribution layer(108) is located between the first redistribution layer(15/14 of Zhang) and the heat dissipation base(110); a chip(104) disposed between the second redistribution layer(108) and the first redistribution layer(15/14 of Zhang), wherein the chip(104) has an active surface(518/520) facing the first redistribution layer(15/14 of Zhang), and the active surface(518/520) is electrically connected to the first redistribution layer(15/14 of Zhang);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Zhang to the teachings of Liu in order to achieve better performance, greater miniaturization, and higher reliability [0002, Zhang]. In doing so, and the second redistribution layer(108) is located between the first redistribution layer(15/14 of Zhang) and the heat dissipation base(110); a chip(104) disposed between the second redistribution layer(108) and the first redistribution layer(15/14 of Zhang), wherein the chip(104) has an active surface(518/520) facing the first redistribution layer(15/14 of Zhang), and the active surface(518/520) is electrically connected to the first redistribution layer(15/14 of Zhang);
Liu and Zhang do not disclose a metal stack (Sp/Sc of Lee); the metal inner core and the metal outer layer(120 of Lee) are partially removed so that the metal inner core is partially exposed on the metal outer layer to be in contact with the second redistribution layer(RDL of Lee); and an encapsulant(
Lee discloses a metal stack (Sp/Sc of Lee); the metal inner core and the metal outer layer(120 of Lee) are partially removed so that the metal inner core is partially exposed on the metal outer layer to be in contact with the second redistribution layer(RDL of Lee); and an encapsulant(130 of Lee) ; a metal stack (Sp/Sc of Lee) disposed between the second redistribution layer(108) and the inactive surface(surface inactive to 216), and the inactive surface(surface inactive to 216) is thermally coupled to the second redistribution layer(108) via the metal stack(Sp/Sc of Lee); the metal inner core and the metal outer layer(120 of Lee) are partially removed so that the metal inner core is partially exposed on the metal outer layer to be in contact with the second redistribution layer(RDL of Lee); and an encapsulant(130 of Lee) filled between the second redistribution layer(108) and the first redistribution layer(210/102).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lee to the teachings of Liu in order to achieve dissipation heat of a semiconductor chip and suppressing warpage of the semiconductor chip [0001, Lee]. In doing so, a metal stack (Sp/Sc of Lee) disposed between the second redistribution layer(108) and the inactive surface(surface inactive to 216), and the inactive surface(surface inactive to 216) is thermally coupled to the second redistribution layer(108) via the metal stack(Sp/Sc of Lee); the metal inner core and the metal outer layer(120 of Lee) are partially removed so that the metal inner core is partially exposed on the metal outer layer to be in contact with the second redistribution layer(RDL of Lee); and an encapsulant(130 of Lee) filled between the second redistribution layer(108) and the first redistribution layer(210/102).
Response to Arguments
Applicant’s arguments with respect to claim 1-22, 36 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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