DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of 1-22, 36 in the reply filed on 10/30/25 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park(USPGPUB DOCUMENT: 2016/0190056, hereinafter Park) in view of Tuominen (USPGPUB DOCUMENT: 2018/0130732, hereinafter Tuominen).
Re claim 1 Park discloses in Fig 2, rotated 180 degrees, a chip(206) package structure, comprising: a heat dissipation base(104); a first redistribution layer(210/102); a second redistribution layer(76/78) disposed on the heat dissipation base(104) and thermally coupled to the heat dissipation base(104), and the second redistribution layer(76/78) is located between the first redistribution layer(210/102) and the heat dissipation base(104); a chip(206) disposed between the second redistribution layer(76/78) and the first redistribution layer(210/102), wherein each of the chips(206) has an active surface(surface active to 216) facing the first redistribution layer(210/102) and an inactive surface(surface active to 216) facing the second redistribution layer(76/78), and the active surfaces(surface active to 216) of the chips(206) are electrically connected to the second redistribution layer(76/78); wherein the inactive surfaces(surface inactive to 216) of the chips(206) are thermally coupled to the second redistribution layer(76/78); a plurality of conductive structures disposed between the second redistribution layer(76/78) and the first redistribution layer(210/102) and electrically connected to the second redistribution layer(76/78) and the first redistribution layer(210/102), wherein each of the conductive structures comprises a metal inner core(220) and a metal outer layer(222) covering the metal inner core(220), and the metal inner core(220) is partially exposed on the metal outer layer(222) to be in contact(by way of 212/214/224) with the second redistribution layer(76/78);
Park does not disclose a plurality of chips(206) disposed between the second redistribution layer(76/78) and the first redistribution layer(210/102) and having different thicknesses; a plurality of metal stacks disposed between the second redistribution layer(76/78) and the inactive surfaces(surface inactive to 216) of the chips(206), wherein the inactive surfaces(surface inactive to 216) of the chips(206) are thermally coupled to the second redistribution layer(76/78) via the metal stacks, and the metal stacks have different thicknesses; and an encapsulant filled between the second redistribution layer(76/78) and the first redistribution layer(210/102).
Tuominen discloses in Fig 9 a plurality of chips(108/109 of Tuominen) having different thicknesses[0030 of Tuominen]; a plurality of metal stacks(148/142 of Tuominen), and the metal stacks have different thicknesses(148/142 of Tuominen); and an encapsulant (156 of Tuominen)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Tuominen to the teachings of Park in order to achieve better performance, greater miniaturization, and higher reliability [0002, Tuominen]. In doing so, a plurality of chips(108/109 of Tuominen) disposed between the second redistribution layer(76/78) and the first redistribution layer(210/102) and having different thicknesses[0030 of Tuominen]; a plurality of metal stacks(148/142 of Tuominen) disposed between the second redistribution layer(76/78) and the inactive surfaces(surface inactive to 216) of the chips(206), wherein the inactive surfaces(surface inactive to 216) of the chips(206) are thermally coupled to the second redistribution layer(76/78) via the metal stacks(148/142 of Tuominen), and the metal stacks have different thicknesses(148/142 of Tuominen); and an encapsulant (156 of Tuominen) filled between the second redistribution layer(76/78) and the first redistribution layer(210/102).
Re claim 2 Park and Tuominen disclose the chip(206) package structure of claim 1, wherein each of the metal stacks(148/142 of Tuominen) comprises a first metal layer and a second metal layer, the first metal layer is located between the second redistribution layer(76/78) and the second metal layer, and the second metal layer is located between the first metal layer and the inactive surface(surface active to 216) of the corresponding chip(206).
Re claim 3 Park and Tuominen disclose the chip(206) package structure of claim 2, wherein the first metal layers of the metal stacks(148/142 of Tuominen) have different thicknesses.
Re claim 4 Park and Tuominen disclose the chip(206) package structure of claim 3, wherein a thickness of the first metal layer of one of the metal stacks(148/142 of Tuominen) connected to one of the thicker chips(206) is less than a thickness of the first metal layer of another metal stack connected to another thinner chip(206).
Re claim 5 Park and Tuominen disclose the chip(206) package structure of claim 3, wherein a total thickness of one of the chips(206) and one of the metal stacks(148/142 of Tuominen) connected to each other is equal to a total thickness of another chip(206) and another metal stack connected to each other.
Re claim 6 Park and Tuominen disclose the chip(206) package structure of claim 2, wherein the second metal layers of the metal stacks(148/142 of Tuominen) have a same thickness.
Re claim 7 Park and Tuominen disclose the chip(206) package structure of claim 2, wherein a material of the first metal layer of each of the metal stacks(148/142 of Tuominen) comprises copper, and a material of the second metal layer comprises tin.
Re claim 8 Park and Tuominen disclose the chip(206) package structure of claim 1, wherein the metal outer layer(222) of each of the conductive structures has a first contact surface in contact with the secondredistribution layer, the metal inner core(220) has a second contact surface exposed to the first contact surface, and the second contact surface is in contact with the second redistribution layer(76/78).
Re claim 9 Park and Tuominen disclose the chip(206) package structure of claim 8, wherein the first contact surface of the metal outer layer(222) of each of the conductive structures and the second contact surface of the metal inner core(220) are coplanar.
Re claim 10 Park and Tuominen disclose the chip(206) package structure of claim 8, wherein the first contact surface of the metal outer layer(222) of each of the conductive structures surrounds the second contact surface of the metal inner core(220).
Re claim 11 Park and Tuominen disclose the chip(206) package structure of claim 1, wherein the metal outer layer(222) of each of the conductive structures is in contact with the first redistribution layer(210/102), and the metal inner core(220) and the first redistribution layer(210/102) are separated by the metal outer layer(222).
Re claim 12 Park and Tuominen disclose the chip(206) package structure of claim 1, wherein each of the conductive structures is a conductive ball or a conductive pillar(see Fig 2 of Park).
Re claim 13 Park and Tuominen disclose the chip(206) package structure of claim 1, wherein a material of the metal inner core(220) of each of the conductive structures is copper, and a material of the metal outer layer(222) is tin.
Re claim 14 Park and Tuominen disclose the chip(206) package structure of claim 1, wherein a material of the heat dissipation base(104) comprises copper or silicon.
Re claim 15 Park and Tuominen disclose the chip(206) package structure of claim 1, further comprising: a plurality of underfill layers respectively disposed between the active surfaces(surface active to 216) of the chips(206) and the first redistribution layer(210/102).
Re claim 16 Park and Tuominen disclose the chip(206) package structure of claim 15, wherein each of the chips(206)also has a side surface connected to the active surface(surface active to 216), and the underfill layer further covers the side surface of the chip(206) and covers the metal stack.
Re claim 17 Park and Tuominen disclose the chip(206) package structure of claim 1, further comprising a third redistribution layer[0054,0055 of Tuominen], wherein the third redistribution layer[0054,0055 of Tuominen] is disposed on the first redistribution layer(210/102), and the first redistribution layer(210/102) is located between the encapsulant and the third redistribution layer[0054,0055 of Tuominen].
Re claim 18 Park and Tuominen disclose the chip(206) package structure of claim 17, wherein the third redistribution layer[0054,0055 of Tuominen] comprises a molding layer covering the first redistribution layer(210/102), at least two circuits[0031 of Tuominen] disposed on the molding layer, and at least two conductive vias penetrating through the molding layer, and the two circuits[0031 of Tuominen] are respectively electrically connected to the first redistribution layer(210/102) via the two conductive vias.
Re claim 19 Park and Tuominen disclose the chip(206) package structure of claim 17, wherein the third redistribution layer[0054,0055 of Tuominen] comprises a first molding layer covering the first redistribution layer(210/102), a second molding layer disposed above the first molding layer, a dielectric layer[0055 of Tuominen] and a first circuit disposed between the first molding layer and the second molding layer, a second circuit and a third circuit disposed on the second molding layer, a first conductive via, a second conductive via, and a third conductive via, the first conductive via penetrates through the first molding layer, and the first circuit is electrically connected to the first redistribution layer(210/102) via the first conductive via, the second conductive via and the third conductive via penetrate through the second molding layer, the dielectric layer[0055 of Tuominen], and the first molding layer, and the second circuit and the third circuit are electrically connected to the first redistribution layer(210/102) via the second conductive via and the third conductive via respectively.
Re claim 20 Park and Tuominen disclose the chip(206) package structure of claim 17, wherein the third redistribution layer[0054,0055 of Tuominen] comprises a molding layer disposed above the first redistribution layer(210/102), at least two circuits[0031 of Tuominen] disposed at a side of the molding layer, at least two conductive vias penetrating through the molding layer, and at least two conductive pads and at least two conductive balls disposed at another side of the molding layer, and the two conductive balls are located between the first redistribution layer(210/102) and the two conductive pads, and each of the circuits[0031 of Tuominen] is electrically connected to the first redistribution layer(210/102) via one of the conductive vias, one of the conductive pads, and one of the conductive balls.
Re claim 21 Park and Tuominen disclose the chip(206) package structure of claim 1, wherein the heat dissipation base(104) comprises a plurality of heat dissipation portions and a plurality of electrical transmission portions, the heat dissipation portions are respectively located opposite to the chips(206) and thermally coupled to the second redistribution layer(76/78), and the electrical transmission portions are located in a periphery of the heat dissipation portions, wherein the electrical transmission portions are respectively located opposite to the conductive structures and electrically connected to the second redistribution layer(76/78).
Re claim 22 Park and Tuominen disclose the chip(206) package structure of claim 1, wherein each of the metal stacks(148/142 of Tuominen) comprises a metal layer and a sintered material layer[0046 of Tuominen], wherein the metal layer is located between the second redistribution layer(76/78) and the sintered material layer[0046 of Tuominen], and the sintered material layer[0046 of Tuominen] is located between the metal layer and the inactive surface(surface active to 216) of the corresponding chip(206).
Claim(s) 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park(USPGPUB DOCUMENT: 2016/0190056, hereinafter Park) in view of Lee (USPGPUB DOCUMENT: 2018/0358288, hereinafter Lee).
Re claim 36 Park discloses in Fig 2, rotated 180 degrees, a chip(206) package structure, comprising: a heat dissipation base(104); a first redistribution layer(210/102); a second redistribution layer(76/78) disposed on the heat dissipation base(104) and thermally coupled to the heat dissipation base(104), and the second redistribution layer(76/78) is located between the first redistribution layer(210/102) and the heat dissipation base(104); a chip(206) disposed between the second redistribution layer(76/78) and the first redistribution layer(210/102), wherein the chip(206) has an active surface(surface active to 216) facing the first redistribution layer(210/102) and an inactive surface (surface inactive to 216) facing the second redistribution layer(76/78), and the active surface(surface active to 216) is electrically connected to the second redistribution layer(76/78); a plurality of conductive structures disposed between the second redistribution layer(76/78) and the first redistribution layer(210/102) and electrically connected to the second redistribution layer(76/78) and the first redistribution layer(210/102), wherein each of the conductive structures comprises a metal inner core(220) and a metal outer layer(222) covering the metal inner core,
Park does not disclose a metal stack disposed between the second redistribution layer(76/78) and the inactive surface(surface inactive to 216), and the inactive surface(surface inactive to 216) is thermally coupled to the second redistribution layer(76/78) via the metal stack; the metal inner core and the metal outer layer(222) are partially removed so that the metal inner core is partially exposed on the metal outer layer(222) to be in contact with the second redistribution layer(76/78); and an encapsulant filled between the second redistribution layer(76/78) and the first redistribution layer(210/102).
Lee discloses a metal stack (Sp/Sc of Lee); the metal inner core and the metal outer layer(120 of Lee) are partially removed so that the metal inner core is partially exposed on the metal outer layer to be in contact with the second redistribution layer(RDL of Lee); and an encapsulant(130 of Lee)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lee to the teachings of Park in order to achieve dissipation heat of a semiconductor chip and suppressing warpage of the semiconductor chip [0001, Lee]. In doing so, a metal stack (Sp/Sc of Lee) disposed between the second redistribution layer(76/78) and the inactive surface(surface inactive to 216), and the inactive surface(surface inactive to 216) is thermally coupled to the second redistribution layer(76/78) via the metal stack(Sp/Sc of Lee); the metal inner core and the metal outer layer(120 of Lee) are partially removed so that the metal inner core is partially exposed on the metal outer layer to be in contact with the second redistribution layer(RDL of Lee); and an encapsulant(130 of Lee) filled between the second redistribution layer(76/78) and the first redistribution layer(210/102).
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812