DETAILED ACTION/EXAMINER’S COMMENT
This Office action responds to the application filed on 07/06/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 03/12/2026 in reply to the non-final rejection mailed on 12/19/2025, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Claim 2 is cancelled. Accordingly, pending in this Office action are claims 1 & 3-20.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-12, & 17-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tanaka (US 20200075486).
Regarding Claim 1, Tanaka (see, e.g., fig. 2) shows an electronic component comprising:
a chip 2 that has a main surface 3;
an insulating layer 13, 14, 15, & 16
that is laminated at a thickness exceeding 2200 nm (see, e.g., para.0065) on the main surface
and has a first end 3 (also at the main surface) on the chip side
and a second end (top surface of 16) on an opposite side to the chip;
and a resistive film 10 that is arranged inside the insulating layer such as not to be positioned within a thickness range of less than 2200 nm on a basis of the first end (see, e.g., para.0058, para.0065)
and includes an alloy crystal constituted of
a metal element
and a nonmetal element (see, e.g., para.0221, para.0223).
wherein the resistive film has a thickness of not less than 0.1 nm and not more than 100 nm (TR, see, e.g., para.0085)
a sheet resistance of the resistive film is not less than 100 Ω/☐ and not more than 10000 Ω/☐ (see, e.g., para.0082)
Regarding the limitations:
an insulating layer 13, 14, 15, & 16
that is laminated at a thickness exceeding 2200 nm (see, e.g., para.0065) on the main surface
and a resistive film 10 that is arranged inside the insulating layer such as not to be positioned within a thickness range of less than 2200 nm on a basis of the first end
Tanaka (see, e.g., para.0065) states each layer 13, 14, 15, & 16 may be not less than 100 nm and not more than 3500 nm. These ranges of thickness would satisfy the limitation of “exceeding 2200 nm” and would arrange the resistive film 10 such as not to be positioned within a thickness range less than 2200 nm. Thus, Tanaka anticipates the claim.
Regarding Claim 3, Tanaka (see, e.g., fig. 2, para.0065) shows electronic component according to Claim 1, further comprising:
an insulating region (between elements 41 & 42) that has only an insulator in a thickness direction of the insulating layer
and is formed to a thickness of not less than 2200 nm inside the insulating layer;
wherein the resistive film is arranged inside the insulating layer such as to cover the insulating region (see, e.g., fig. 2).
Regarding Claim 4, Tanaka (see, e.g., fig. 2, para.0185-0188) . The electronic component according to Claim 1, further comprising:
a plurality of wirings 41, 42, & 95 that are laminated
and arranged in a thickness direction of the insulating layer
within a thickness range between the main surface 3 and the resistive film inside the insulating layer (see, e.g., fig. 2).
Regarding Claim 5, Tanaka (see, e.g., fig. 2) shows the electronic component according to Claim 4,
wherein the plurality of wirings are not arranged
within a thickness range between the second end and the resistive film inside the insulating layer (see, e.g., fig. 2).
Regarding Claim 6, Tanaka shows the electronic component according to Claim 1,
wherein a thickness (thickness of layers 13, 14, & 15) between the first end 3 and the resistive film 10 inside the insulating layer
is not less than a thickness (thickness of layer 16) between the second end (top surface of 16) and the resistive film inside the insulating layer.
Tanaka (see, e.g., para.0065) states each layer 13, 14, 15, & 16 may be not less than 100 nm and not more than 3500 nm. The thickness of layers 13, 14, & 15 would not be less than the thickness of layer 16. Thus, Tanaka anticipates the claim.
Regarding Claim 7. The electronic component according to Claim 1,
wherein the insulating layer has a thickness exceeding 3100 nm,
and the resistive film is arranged inside the insulating layer such as not to be positioned
within a thickness range of less than 3100 nm on the basis of the first end.
Tanaka (see, e.g., para.0065) states the insulating layer and each of its layers 13, 14, 15, & 16 may be not less than 100 nm and not more than 3500 nm. These ranges of thickness would satisfy the limitation of “exceeding 3100 nm” and would arrange the resistive film such as not to be positioned within a thickness range less than 3100 nm. Thus, Tanaka anticipates the claim.
Regarding Claim 8, Tanaka (see, e.g., fig. 2, para.0059-0060) shows the electronic component according to Claim 1,
wherein the insulating layer has a laminated structure including not less than three layers of interlayer insulating films,
and the resistive film is arranged on the interlayer insulating film of the third layer or higher.
Regarding Claim 9, Tanka (see, e.g., fig. 2, para.0059-0060) shows the electronic component according to Claim 8,
wherein the insulating layer includes not less than four layers of the interlayer insulating films, and the resistive film is arranged on the interlayer insulating film of the fourth layer or higher.
Regarding Claim 10, Tanaka (see, e.g., fig. 2, para.0065) shows the electronic component according to Claim 8,
wherein each of the interlayer insulating films has a thickness of not less than 100 nm and not more than 3000 nm.
Regarding Claim 11, Tanaka (see, e.g., fig. 2, para.0142) shows the electronic component according to Claim 1, further comprising:
a top wiring 61 & 62 that is arranged on the second end.
Regarding Claim 12, Tanaka (see, e.g., fig. 2, para.0195) shows the electronic component according to Claim 11, further comprising:
a top insulating layer 101 that partially covers the top wiring.
Regarding Claim 17, Tanaka (see, e.g., para.0199) shows the electronic component according to Claim 1,
wherein the resistive film includes at least one among a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film.
Regarding Claim 18, Tanaka (see, e.g., fig. 2) shows an electronic component comprising:
a chip 2 that has a main surface 3;
an insulating layer 13, 14, 15, & 16 that is laminated at a thickness exceeding 2200 nm (see, e.g., para.0065) on the main surface
and has a first end 3 (also at the main surface) on the chip side
and a second end (top surface of 16) on an opposite side to the chip;
an insulating region that has only an insulator in a thickness direction of the insulating layer
and is formed to a thickness of not less than 2200 nm inside the insulating layer;
and a resistive film 10 (see, e.g., para.0058, para.0065) that is arranged in a region between the second end and the insulating region inside the insulating layer such as to directly cover the insulating region
and includes an alloy crystal constituted of
a metal element
and a nonmetal element (see, e.g., para.0221, para.0223).
wherein the resistive film has a thickness of not less than 0.1 nm and not more than 100 nm (TR, see, e.g., para.0085)
a sheet resistance of the resistive film is not less than 100 Ω/☐ and not more than 10000 Ω/☐ (see, e.g., para.0082)
Regarding Claim 19, Tanaka (see, e.g., fig. 1, para.0125) shows the electronic component according to Claim 18, further comprising:
a first wiring 41 that is arranged inside the insulating layer;
and a second wiring 42 that is arranged at an interval from the first wiring in plan view inside the insulating layer;
wherein the insulating region is demarcated in a region between the first wiring and the second wiring in plan view (see, e.g., fig. 1),
and the resistive film is arranged inside the insulating layer such as to directly cover the insulating region and overlap with the first wiring and the second wiring in plan view.
Regarding Claim 20, Tanaka (see, e.g., fig. 2, para.0069) shows the electronic component according to Claim 19, further comprising:
a first via electrode 23 that is arranged between the resistive film and the first wiring inside the insulating layer;
and a second via electrode 24 that is arranged between the resistive film and the second wiring inside the insulating layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka (US 20200075486) in view of Iida (US 6287933).
Regarding Claim 13, Tanaka, shows the electronic component according to Claim 1.
Tanaka, however, fails to show
wherein a first order coefficient of a temperature coefficient of resistance of the resistive film is not less than -20 ppm/°C and not more than +60 ppm/°C.
Iida (see, e.g., fig. 12, pg. 24, col. 6, ll. 1-6) in a device similar to Tanaka, teaches a resistive film made of CrSiN, wherein values of the first order coefficient of the temperature coefficient resistance of the resistive film would be within the claimed range of not less than -20 ppm/°C and not more than +60 ppm/°C. The first order coefficient of Iida’s resistive film is dependent on the composition percentage of Si, Cr, and N within the resistive film and is adjustable by the film’s composition. Thus, the first order coefficient values of Iida would be obvious and expected results by routine experimentation.
It would have been obvious to one of ordinary skill in the art to use the first order coefficient values of Iida, because the first order coefficient of temperature coefficient resistance is a known result-effective variable shown by routine experimentation of the resistive film’s composition. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Although Applicant has established criticality and provided data for the criticality of Claim 1’s limitation “a thickness exceeding 2200 nm” and the position of the resistive film (see, e.g., Applicant’s Specification, fig. 7, para.0078-0084), Claim 13’s first order coefficient range is a byproduct of the thickness and the position of the resistive film. The data provided (see, e.g., Applicant’s Specification, fig. 8, para.0085-0092) does not demonstrate that the claimed first order coefficient range produces unexpected results independent of the thickness and the position of the resistive film. Therefore the claimed first order coefficient range is not interpreted as a critical feature of the invention, and Claim 13 would have been obvious to one of ordinary skill in the art at the time of the invention.
Regarding Claim 14, Tanaka, in view of Iida (see, e.g., fig. 12, pg. 24, col. 6, ll. 1-6), shows the electronic component according to Claim 13,
wherein the first order coefficient is not more than +25 ppm/°C.
Regarding Claim 15, Tanaka shows the electronic component according to Claim 1,
wherein a second order coefficient of a temperature coefficient of resistance of the resistive film is not less than -0.23 ppm/°C2 and not more than -0.08 ppm/°C2.
Iida (see, e.g., fig. 12, pg. 24, col. 6, ll. 1-6) in a device similar to Tanaka, teaches a resistive film made of CrSiN, wherein values of the second order coefficient of the temperature coefficient resistance of the resistive film would be within the claimed range of not less than -0.23 ppm/°C2 and not more than -0.08 ppm/°C2. The second order coefficient of Iida’s resistive film is dependent on the composition percentage of Si, Cr, and N within the resistive film and is adjustable by the film’s composition. Thus, the second order coefficient values of Iida would be obvious and expected results by routine experimentation.
It would have been obvious to one of ordinary skill in the art to use the second order coefficient values of Iida, because the second order coefficient of temperature coefficient resistance is a known result-effective variable shown by routine experimentation of the resistive film’s composition. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Although Applicant has established criticality and provided data for the criticality of Claim 1’s limitation “a thickness exceeding 2200 nm” and the position of the resistive film (see, e.g., Applicant’s Specification, fig. 7, para.0078-0084), Claim 15’s second order coefficient range is a byproduct of the thickness and the position of the resistive film. The data provided (see, e.g., Applicant’s Specification, fig. 8, para.0085-0092) does not demonstrate that the claimed second order coefficient range produces unexpected results independent of the thickness and the position of the resistive film. Therefore the claimed second order coefficient range is not interpreted as a critical feature of the invention, and Claim 15 would have been obvious to one of ordinary skill in the art at the time of the invention.
Regarding Claim 16, Tanaka, in view of Iida (see, e.g., fig. 12, pg. 24, col. 6, ll. 1-6), shows the electronic component according to Claim 15,
wherein the second order coefficient is not less than -0.16 ppm/°C2.
Response to Amendments
Regarding the amended limitations of claims 1 & 18, “wherein the resistive film has a thickness of not less than 0.1 nm and not more than 100 nm, and a sheet resistance of the resistive film is not less than 100 Ω/☐ and not more than 10000 Ω/☐,” the prior art of record (Tanaka) does anticipate the limitations.
Tanaka (see, e.g., para.0084-0085) states the resistive film 10 has a thickness TR not less than 0.1 nm and not more than 100 nm.
Tanaka (see, e.g., para.0082) states “a sheet resistance value of the resistance layer 10 may be not less than 100 Ω/☐ and not more than 5000 Ω/☐” which is within the claimed range of the amended limitation. See MPEP 2131.03(I) "If the prior art discloses a point within the claimed range, the prior art anticipates the claim." UCB, Inc. v. Actavis Labs. UT, Inc., 65 F.4th 679, 687, 2023 USPQ2d 448 (Fed. Cir. 2023).
Response to Arguments
Applicant’s arguments, see page 8, filed 03/12/2026, with respect to the rejection of claim 5 under 35 U.S.C. 112(b) has been fully considered and is persuasive. The rejection of claim 5 under 35 U.S.C. 112(b) has been withdrawn.
Applicant's arguments, see pages 8-13 have been fully considered but they are not persuasive. The prior art of record overcomes the amendments of claims 1 & 18 and the rejections of 1 & 3-20 withstand.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO JOSE RAMOS-DIAZ/Examiner, Art Unit 2818 /STEVEN H LOKE/ Supervisory Patent Examiner, Art Unit 2818
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