DETAILED ACTION
This Notice is responsive to communication filed on 05/22/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 05/22/2026 has been acknowledged and entered into the record.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 16, 18, 22, and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishihara et al. (US 20150023016).
Regarding claim 1, Ishihara teaches a light-emitting diode (LED) packaging device, comprising:
a packaging substrate Fig. 26: 11, comprising a mounting surface (top surface), wherein the mounting surface is configured with a metal layer Fig. 26: 12 comprising a die-bonding area Fig. 26: 12a and a non-die-bonding area Fig. 26: 12b (para. 0050);
a LED chip Fig. 26: 2, disposed on the die-bonding area Fig. 26: 12a of the packaging substrate Fig. 26: 11; and
a packaging layer Fig. 26: 3, disposed covering the die-bonding area Fig. 26: 12a and the non-die-bonding area Fig. 26: 12b of the packaging substrate Fig. 26: 11, wherein the LED chip Fig. 26: 2 is located between the packaging layer Fig. 26: 3 and the packaging substate Fig. 26: 11, the packaging layer Fig. 26: 3 around the LED chip Fig. 26: 2 is configured with a stepped structure Fig. 26: 31, steps of the stepped structure Fig. 26: 31 are sequentially defined as a first step, a second step, until an nth step in an order from top to bottom, n is an integer greater than or equal to 2; each of the steps comprises a step surface and a vertical surface, and a maximum horizontal distance between the vertical surface of the first step and the LED chip Fig. 26: 2 is less than a horizontal distance between the vertical surface of the nth step and the LED chip Fig. 26: 2 (shown in Fig. 26);
wherein a side surface of the non-die-bonding area Fig. 26: 12b facing away from the LED chip Fig. 26: 2 is flush with the vertical surface of the second step (shown in Fig. 26); an upper surface of the non-die-bonding area Fig. 26: 12b is fully covered with the packaging layer Fig. 26: 3; and an isolation groove (spacing between 12a and 12b) is disposed between the die-bonding area Fig. 26: 12a and the non-die- bonding area Fig. 26: 12b to electrically isolate the die-bonding area Fig. 26: 12a from the non-die-bonding area Fig. 26: 12b and is filled with the packaging layer Fig. 26: 3 (shown in Fig. 26; para. 0051).
Regarding claim 16, Ishihara teaches the LED packaging device according to claim 1, wherein the LED chip Fig. 26: 2 is configured to emit light with a wavelength of less than 400 nanometers (nm) (para. 0084 teaches the LED chip emits blue light which falls within the range of claim 16).
Regarding claim 18, Ishihara teaches the LED packaging device according to claim 1, wherein an upper surface of the LED chip Fig. 26: 2 facing away from the packaging substrate Fig. 26: 11 is located between the step surface of the first step (annotated) and the step surface of the second step (annotated) and thus the step surface of the second step (annotated) is lower than the upper surface of the LED chip Fig. 26: 2 (this is shown in Fig. 26).
PNG
media_image1.png
585
443
media_image1.png
Greyscale
Regarding claim 22, Ishihara teaches the LED packaging device according to claim 1, wherein a minimum vertical distance between the step surface of the first step and the LED chip Fig. 26: 2 is a first thickness (annotated T1), a minimum horizontal distance between the vertical surface of the first step and the LED chip Fig. 26: 2 is a second thickness (annotated T2), and the first thickness is less than the second thickness (shown in Fig. 26, annotated).
PNG
media_image2.png
283
391
media_image2.png
Greyscale
Regarding claim 23, Ishihara teaches the LED packaging device according to claim 1, wherein a horizontal distance between a side surface of the non-die-bonding area facing towards the isolation groove and the LED chip is less than the horizontal distance between the vertical surface of the second step and the LED chip.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference(s).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ishihara et al. (US 20150023016) as applied to claim 1 above, and further in view of Okamura et al. (US 20090057698).
Regarding claim 3, Okamura teaches the following claim limitations not disclosed by Ishihara: The LED packaging device according to claim 1:
wherein a roughness of the vertical surface is greater than 100 micrometers (μm) (para. 0030, “0.5-150 mu.m”).
Okamura teaches a ceramic phosphor layer Fig. 1: 11 having an outer surface with average surface roughness of 0.5-150 mu.m (also see para. 0032).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Ishihara with Okamura for the purpose of preventing scattering at the outer surface (para. 0032) and obtaining a higher luminous intensity (para. 0030).
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Ishihara et al. (US 20150023016) as applied to claim 1 above, and further in view of Lee et al. (US 20160276546).
Regarding claim 4, Ishihara teaches the LED packaging device according to claim 1 wherein:
a minimum vertical distance between the step surface of the first step and the LED chip Fig. 26: 3 is a first thickness (annotated T1),
a minimum horizontal distance between the vertical surface of the first step and the LED chip Fig. 9C: 20 is a second thickness (annotated T2), and
a ratio of the first thickness to the second thickness is in a range of 1:5 to 3:1 (para. 0038).
Lee teaches the following claim limitations not disclosed by Ishihara:
a ratio of the first thickness to the second thickness is in a range of 1:5 to 3:1 (para. 0038).
Lee teaches a thickness of the fluorescent layer (44 in Fig. 9C) ranging between 100 – 250 µm which falls within the range taught by claim 4 of the present application (see Specification para. 0055, teaching a range of D1 from 100-300µm, D2 from 100-500µm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Ishihara with Lee for the purpose of adjusting the thickness of the fluorescent layer based on different demands for the degrees of color temperatures to be achieved to obtain the preferred light conversion and extraction efficiency, improving flexibility in application variations of the LED package (para. 0038).
PNG
media_image3.png
512
771
media_image3.png
Greyscale
Regarding claim 5, Ishihara teaches the LED packaging device according to claim 4, wherein:
a vertical distance between the step surface of the nth step and the mounting surface of the packaging substrate is a third thickness, and
a ratio of the first thickness to the third thickness is in a range of 1:4 to 3:1.
Lee teaches the following claim limitations not disclosed by Ishihara:
a ratio of the first thickness (annotated above) to the third thickness (annotated above) is in a range of 1:4 to 3:1 (para. 0038).
Lee teaches a thickness of the fluorescent layer (44 in Fig. 9C) ranging between 100 – 250 µm which falls within the range taught by claim 5 of the present application (see Specification para. 0055, teaching a range of D1 from 100-300µm, D2 from 100-500µm, D3 from 100-400µm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Ishihara with Lee for the purpose of adjusting the thickness of the fluorescent layer based on different demands for the degrees of color temperatures to be achieved to obtain the preferred light conversion and extraction efficiency, improving flexibility in application variations of the LED package (para. 0038).
Regarding claim 6, Lee teaches the following claim limitations not disclosed by Ishihara:
The LED packaging device according to claim 5, wherein
a thickness of the fluorescent layer (44 in Fig. 9C) ranging between 100 – 250 µm which falls within the range taught by claim 6 of the present application (see Specification para. 0055, teaching a range of D1 from 100-300µm, D2 from 100-500µm, D3 from 100-400µm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Ishihara with Lee for the purpose of adjusting the thickness of the fluorescent layer based on different demands for the degrees of color temperatures to be achieved to obtain the preferred light conversion and extraction efficiency, improving flexibility in application variations of the LED package (para. 0038).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Ishihara et al. (US 20150023016) and Lee et al. (US 20160276546) as applied to claim 6 above, and further in view of Tanimoto et al. (JP 2007042749 A).
Regarding claim 7, Tanimoto teaches the following claim limitations not disclosed by Ishihara and Lee:
the LED packaging device according to claim 6, wherein,
a thickness of the LED chip Fig. 1: 13 is in a range of 200µm to 400µm (para. 0023 teaches range of 0.01-0.5mm, which is about 10-500µm and includes range taught by claim 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Ishihara and Lee with Tanimoto for the purpose of having a constant shape to reduce color unevenness of the emitted color (para. 0013).
Regarding claim 8, Tanimoto teaches the following claim limitations not disclosed by Ishihara and Lee:
the LED packaging device according to claim 6, wherein,
a range of 400μm to 700μm (para. 0023 teaches range of 0.01-0.5mm, which is about 10-500µm and includes range taught by claim 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Ishihara and Lee with Tanimoto for the purpose of having a constant shape to reduce color unevenness of the emitted color (para. 0013).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ishihara et al. (US 20150023016) as applied to claim 1 above, and further in view of Tanimoto et al. (JP 2007042749 A).
Regarding claim 10, Tanimoto teaches the following claim limitations not disclosed by Ishihara and Lee:
the LED packaging device according to claim 6, wherein
angles between the vertical surface of each of all the steps except for the nth step and the step surfaces adjacent thereto are 90° (as shown in Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Ishihara with Tanimoto such that the stepped portion of the light emitting device has an optical path length of light emission in the parallel and perpendicular directions to the substrate can be made constant, so that the color unevenness of the light emission color at the upper and side surfaces of the phosphor layer (i.e. package layer) can be reduced (para. 0014-0015).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Ishihara et al. (US 20150023016) as applied to claim 1 above, and further in view of Nakatsu et al. (JP 2009158655 A).
Regarding claim 17, Nakatsu teaches the following claim limitations not disclosed by Ishihara:
the LED packaging device according to claim 1, wherein
a material of the packaging layer Fig. 1/2: 14 comprises a fluorine-containing material (para. 0008).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Ishihara with Nakatsu for the purpose of ensuring high adhesion with the boundary surface of the substrate, ensuring high reliability, while maintaining the low hygroscopicity and weather resistance of the fluorine-based resin (para. 0008).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Ishihara et al. (US 20150023016) as applied to claim 1 above, and further in view of Janducayan et al. (US 20090166826).
Regarding claim 21, Janducayan teaches the following claim limitations not disclosed by Ishihara:
the LED packaging device according to claim 1, wherein
a thickness of the metal layer Fig. 2: 20 is in a range of 50-200µm.
Janducayan teaches a thickness of a die paddle (para. 0015), which is a part of the metal leadframe 10, where the die is disposed on, is between 100 to 250 microns, which is inclusive of the range taught by claim 21.
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ishihara with Janducayan to have a metal layer with the claimed thickness (para. 0015), which is typical of leadframes that accommodate thin chips operating at high speed (para. 0019).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
Prosecution Insights