DETAILED ACTION
This Notice is responsive to communication filed on 02/11/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1, reading on Fig. 1 in the reply filed on 02/11/2026 is acknowledged.
Claims 2, 9, 11-15, an 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/11/2026.
Claims 2, 9, 11-15, an 19-20 have been cancelled in the reply filed on 02/11/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/06/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xiao et al. (CN 211742531 U).
Regarding claim 1, Xiao teaches a light-emitting diode (LED) packaging device, comprising:
a packaging substrate Fig. 3: 21, comprising a mounting surface (annotated below), wherein the mounting surface is configured with a die-bonding area and a non-die-bonding area (annotated below);
a LED chip Fig. 3: 22, disposed on the die-bonding area of the packaging substrate Fig. 3: 21; and
a packaging layer Fig. 3: 23, disposed covering the die-bonding area and the non-die-bonding area of the packaging substrate Fig. 3: 21, wherein the LED chip Fig. 3: 22 is located between the packaging layer Fig. 3: 23 and the packaging substate Fig. 3: 21, the packaging layer Fig. 3: 23 around the LED chip Fig. 3: 22 is configured with a stepped structure, steps of the stepped structure are sequentially defined as a first step, a second step, until an nth step in an order from top to bottom, n is an integer greater than or equal to 2; each of the steps comprises a step surface and a vertical surface, and a maximum horizontal distance between the vertical surface of the first step and the LED chip Fig. 3: 22 is less than a horizontal distance between the vertical surface of the nth step and the LED chip Fig. 3: 22 (see annotated below).
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Regarding claim 18, Xiao teaches the LED packaging device according to claim 1, wherein an upper surface of the LED chip Fig. 3: 22 facing away from the packaging substrate Fig. 3: 21 is located between the step surface of the first step (annotated step surface 1) and the step surface of the second step (annotated step surface 2) and thus the step surface of the second step (annotated step surface 2) is lower than the upper surface of the LED chip Fig. 3: 22 (this is shown in Fig. 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (CN 211742531) as applied to claim 1 above, and further in view of Okamura et al. (US 20090057698).
Regarding claim 3, although Xiao teaches the substantial features of the claimed invention, Xiao fails to explicitly teach the LED packaging device according to claim 1, wherein a roughness of the vertical surface is greater than 100 micrometers (μm). However, Okamura teaches wherein a roughness of the vertical surface is greater than 100 micrometers (μm) (para. 0030, “0.5-150 mu.m”). Okamura teaches a ceramic phosphor layer Fig. 1: 11 having an outer surface with average surface roughness of 0.5-150 mu.m (also see para. 0032). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Xiao and Okamura for the purpose of preventing scattering at the outer surface (para. 0032) and obtaining a higher luminous intensity (para. 0030).
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (CN 211742531) as applied to claim 1 above, and further in view of Lee et al. (US 20160276546).
Regarding claim 4, although Xiao teaches the substantial features of the claimed invention, Xiao fails to explicitly teach the LED packaging device according to claim 1, wherein a minimum vertical distance between the step surface of the first step and the LED chip is a first thickness, a minimum horizontal distance between the vertical surface of the first step and the LED chip is a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:5 to 3:1. However, Lee teaches wherein a minimum vertical distance between the step surface of the first step and the LED chip Fig. 9C: 20 is a first thickness (annotated below), a minimum horizontal distance between the vertical surface of the first step and the LED chip Fig. 9C: 20 is a second thickness (annotated below), and a ratio of the first thickness to the second thickness is in a range of 1:5 to 3:1 (para. 0038). Lee teaches a thickness of the fluorescent layer (44 in Fig. 9C) ranging between 100 – 250 µm which falls within the range taught by claim 4 of the present application (see Specification para. 0055, teaching a range of D1 from 100-300µm, D2 from 100-500µm). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Xiao and Lee for the purpose of adjusting the thickness of the fluorescent layer based on different demands for the degrees of color temperatures to be achieved to obtain the preferred light conversion and extraction efficiency, improving flexibility in application variations of the LED package (para. 0038).
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Regarding claim 5, although Xiao teaches the substantial features of the claimed invention, Xiao fails to explicitly teach the LED packaging device according to claim 4, wherein a vertical distance between the step surface of the nth step and the mounting surface of the packaging substrate is a third thickness, and a ratio of the first thickness to the third thickness is in a range of 1:4 to 3:1. However, Lee teaches wherein a vertical distance between the step surface of the nth step and the mounting surface of the packaging substrate Fig. 9C: 10 is a third thickness (annotated above), and a ratio of the first thickness (annotated above) to the third thickness (annotated above) is in a range of 1:4 to 3:1 (para. 0038). Lee teaches a thickness of the fluorescent layer (44 in Fig. 9C) ranging between 100 – 250 µm which falls within the range taught by claim 5 of the present application (see Specification para. 0055, teaching a range of D1 from 100-300µm, D2 from 100-500µm, D3 from 100-400µm). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Xiao and Lee for the purpose of adjusting the thickness of the fluorescent layer based on different demands for the degrees of color temperatures to be achieved to obtain the preferred light conversion and extraction efficiency, improving flexibility in application variations of the LED package (para. 0038).
Regarding claim 6, although Xiao teaches the substantial features of the claimed invention, Xiao fails to explicitly teach the LED packaging device according to claim 5, wherein a ratio of the second thickness to the third thickness is in a range of 1:4 to 5:1. However, Lee teaches wherein a ratio of the second thickness (annotated above) to the third thickness (annotated above) is in a range of 1:4 to 5:1 (para. 0038). Lee teaches a thickness of the fluorescent layer (44 in Fig. 9C) ranging between 100 – 250 µm which falls within the range taught by claim 6 of the present application (see Specification para. 0055, teaching a range of D1 from 100-300µm, D2 from 100-500µm, D3 from 100-400µm). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Xiao and Lee for the purpose of adjusting the thickness of the fluorescent layer based on different demands for the degrees of color temperatures to be achieved to obtain the preferred light conversion and extraction efficiency, improving flexibility in application variations of the LED package (para. 0038).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (CN 211742531) and Lee et al. (US 20160276546). as applied to claim 6 above, and further in view of Tanimoto et al. (JP 2007042749 A).
Regarding claim 7, although Xiao and Lee teach the LED packaging device according to claim 6, wherein correspondingly the ratio of the first thickness (annotated Fig. 9C above) to the second thickness (annotated Fig. 9C above) is in a range of 1:5 to 2:1, the ratio of the first thickness (annotated Fig. 9C above) to the third thickness (annotated Fig. 9C above) is in a range of 1:2 to 2:1, and the ratio of the second thickness (annotated Fig. 9C above) to the third thickness (annotated Fig. 9C above) is in a range of 1:2 to 5:1 (Lee teaches in para. 0038 a thickness of the fluorescent layer (44 in Fig. 9C) ranging between 100 – 250 µm which falls within the range taught by claim 7 of the present application (see Specification para. 0056, teaching a range of D1 from 100-200µm, D2 from 100-500µm, D3 from 100-200µm)), they fail to explicitly teach wherein a thickness of the LED chip is in a range of 200µm to 400µm. However, Tanimoto teaches wherein a thickness of the LED chip Fig. 1: 13 is in a range of 200µm to 400µm (para. 0023 teaches range of 0.01-0.5mm, which is about 10-500µm and includes range taught by claim 7). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Xiao, Lee, and Tanimoto for the purpose of having a constant shape to reduce color unevenness of the emitted color (para. 0013).
Regarding claim 8, although Xiao and Lee teach the LED packaging device according to claim 6, wherein correspondingly the ratio of the first thickness (annotated Fig. 9C above) to the second thickness (annotated Fig. 9C above) is in the range of 1:5 to 3:1, the ratio of the first thickness (annotated Fig. 9C above) to the third thickness (annotated Fig. 9C above) is in the range of 1:4 to 3:1, and the ratio of the second thickness (annotated Fig. 9C above) to the third thickness (annotated Fig. 9C above) is in the range of 1:4 to 5:1 (Lee teaches in para. 0038 a thickness of the fluorescent layer (44 in Fig. 9C) ranging between 100 – 250 µm which falls within the range taught by claim 7 of the present application (see Specification para. 0057, teaching a range of D1 from 100-300µm, D2 from 100-500µm, D3 from 100-400µm)), they fail to explicitly teach wherein a thickness of the LED chip is in a range of 400μm to 700μm. However, Tanimoto teaches wherein a thickness of the LED chip is in a range of 400μm to 700μm (para. 0023 teaches range of 0.01-0.5mm, which is about 10-500µm and includes range taught by claim 8). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Xiao, Lee, and Tanimoto for the purpose of having a constant shape to reduce color unevenness of the emitted color (para. 0013).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (CN 211742531) as applied to claim 1 above, and further in view of Tanimoto et al. (JP 2007042749 A).
Regarding claim 10, although Xiao teaches the substantial features of the claimed invention, Xiao fails to explicitly teach the LED packaging device according to claim 1, wherein angles between the vertical surface of each of all the steps except for the nth step and the step surfaces adjacent thereto are 90°. However, Tanimoto teaches wherein angles between the vertical surface of each of all the steps except for the nth step and the step surfaces adjacent thereto are 90° (as shown in Fig. 1). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Tanimoto and Xiao such that the stepped portion of the light emitting device has an optical path length of light emission in the parallel and perpendicular directions to the substrate can be made constant, so that the color unevenness of the light emission color at the upper and side surfaces of the phosphor layer (i.e. package layer) can be reduced (para. 0014-0015).
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (CN 211742531) as applied to claim 1 above, and further in view of Shi et al. (US 20210091277).
Regarding claim 16, although Xiao teaches the substantial features of the claimed invention, Xiao fails to explicitly teach the LED packaging device according to claim 1, wherein the LED chip is configured to emit light with a wavelength of less than 400 nanometers (nm). However, Shi teaches wherein the LED chip Fig. 1: 30 is configured to emit light with a wavelength of less than 400 nanometers (para. 0015, i.e. 200-390nm). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Xiao and Shi for the purpose of having a device with an emission wavelength range capable for different practical applications such as surface germicidal irradiation or surface curing (para. 0015).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (CN 211742531) as applied to claim 1 above, and further in view of Nakatsu et al. (JP 2009158655 A).
Regarding claim 17, although Xiao teaches the substantial features of the claimed invention, Xiao fails to explicitly teach the LED packaging device according to claim 1, wherein a material of the packaging layer comprises a fluorine-containing material. However, Nakatsu teaches wherein a material of the packaging layer Fig. 1/2: 14 comprises a fluorine-containing material (para. 0008). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Xiao and Nakatsu for the purpose of ensuring high adhesion with the boundary surface of the substrate, ensuring high reliability, while maintaining the low hygroscopicity and weather resistance of the fluorine-based resin (para. 0008).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 7, 2026