DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II and Species II, claims 1-10, in the reply filed on 01/08/2026 is acknowledged.
IDS
The IDS document(s) filed on 07/06/2023, 01/24/2024, 04/19/2024 and 04/24/2025 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Specification Objection
The disclosure is objected to because of the following informalities: Par. 0063, Line 4 of Applicant’s Specification recites “located in the bridge region 250” (emphasis added), however, it should read “located in the bridge region 240”.
Appropriate correction is required.
Drawing Objections
The drawings are objected to because per Par 0070, Fig. 1C should be L3 for the top tier instead of L1. Additionally, Fig. 1E should read 86C not 86A as it is the cross-section E-E’ of Fig. 1B which indicates 86C. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Ito et al. (US 2021/0242128 A1), hereafter “Ito”.
As to claim 1, Ito teaches a multi-tier memory device, comprising:
a substrate (⁋ [0052], 110, Fig. 1D); and
a plurality of tier structures located at multiple-tier levels that are vertically spaced from the substrate by different vertical spacings (see annotated Fig. 1D below), wherein each of the plurality of tier structures comprises:
backside trench fill structures (⁋ [0052], 76, Figs. 1C+1D) laterally extending through each of the plurality of tier structures along a first horizontal direction (Fig. 1C, hd1), and are laterally spaced apart from each other along a second horizontal direction (hd2);
alternating stacks of insulating layers and electrically conductive layers (⁋ [0051], “alternating stacks of insulating layers (132, 232) and electrically conductive layers (146, 246)”) that are laterally spaced apart from each other along the second horizontal direction (hd2) by the backside trench fill structures (76) (Fig. 1D), laterally extend along the first horizontal direction through an inter-array region (Fig. 1B, 200), a first memory array region (left 100) and a second memory array region (right 100) that is laterally spaced apart along the first horizontal direction (hd1) from the first memory array region by the inter-array region (⁋ [0051], “that extend over all areas of the memory array regions 100 and the inter-array regions 200”); and
memory opening fill structures that vertically extend through each of the plurality of tier structures, wherein each of the memory opening fill structures comprises a respective vertical semiconductor channel and vertical stack of memory elements located at levels of the electrically conductive layers (⁋ [0050]),
wherein:
each of the alternating stacks includes stepped surfaces in the inter-array region (Fig. 1F, ⁋ [0054], “The electrically conductive layers (146, 246) of the alternating stacks are disconnected along the first horizontal direction hd1 in the terrace region 210 located in the inter-array region 200….to provide stepped surfaces (i.e., steps “S”) within each terrace region 210”);
each electrically conductive layer within the alternating stacks has a respective bridge region (220) having a respective strip width along the second horizontal direction (hd2) within the inter-array region (200) (⁋ [0053]), and has a respective uniform width along the second horizontal direction greater than the strip width in the first memory array region, the second memory array region, and portions of the inter-array region located outside the bridge region (Fig. 1C shows a uniform width of 220 only located in a portion of 200; ⁋ [0053] states the bridge region is located in inter-array region 200)( Examiner assumes Applicant is claiming the strip width is only located in the bridge region 240, and no other region, making the respective uniform width greater than the strip width in the other 3 regions indicated. Applicant’s Fig. 1B only shows the bridge region 240, which contains the strip width, located in a portion of 200 therefore the strip width in the other 3 locations indicated would be 0).
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Ito’s previous embodiment fails to teach the strip width of a topmost electrically conductive layer in a first-tier alternating stack is smaller than the strip width of a topmost electrically conductive layer in a second-tier alternating stack which overlies the first-tier alternating stack, however, it is shown in another embodiment of Fig. 1I wherein a subset (S4, ⁋ [0062]) contains a smaller strip width than a subset (T3, ⁋ [0068]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the configuration of Ito’s second embodiment into the previously discussed embodiment because the sidewalls of the first and second patterned in-process alternating stack of insulating layers (132 and 232) and sacrificial material layers that laterally extend along the first horizontal direction hd1 can be patterned in a manner that reduces the total area occupied by the sidewalls of the first patterned in-process alternating stack.
Additionally, electrical conductance of the portions of the electrically conductive layers connecting a first memory array region 100A and a second memory array region 100B can be enhanced (⁋ [0183]).
As to claim 2, Ito teaches the multi-tier memory device of Claim 1, wherein:
each of the backside trench fill structures (76) comprises a dielectric material portion (⁋ [0057], “dielectric wall structures) that continuously extends from a top surface of the substrate to a topmost surface of the plurality of tier structures (Fig 1D).
Ito fails to teach the strip width of a topmost electrically conductive layer in the second-tier alternating stack is smaller than the strip width of a topmost electrically conductive layer in a third-tier alternating stack which overlies the second-tier alternating stack.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to add a third tier on the second tier as already taught by Ito’s second tier on first tier structure, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
As to claim 3, Ito teaches the multi-tier memory device of Claim 1, wherein each of the plurality of tier structures further comprises a respective retro-stepped dielectric material portion which contacts the stepped surfaces in the inter-array region (Fig. 1D, 165+265, ⁋ [0055], “a first retro-stepped dielectric material portion 165 and/or a second retro-stepped dielectric material portion 265”).
As to claim 10, Ito teaches the multi-tier memory device of Claim 3, further comprising layer contact via structures (Fig. 1D, 86, ⁋ [0055]) vertically extending through the retro-stepped dielectric material portions, and contacting a respective one of the electrically conductive layers (⁋ [0055], “can be formed through the dielectric material portion(s) (such as the first retro-stepped dielectric material portion 165 and/or the second retro-stepped dielectric material portion 265) to provide electrical contact to a respective electrically conductive layer”).
Allowable Subject Matter
Claims 4-9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 4 (from which claims 5-9 depend), Ito is the closest prior art and fails to teach wherein: a pair of first retro-stepped dielectric material portions of the retro-stepped dielectric material portions is located at a first-tier level, and comprises a respective pair of bottommost surfaces that are laterally spaced from a first backside trench fill structure of the backside trench fill structures along the second horizontal direction; and a pair of second retro-stepped dielectric material portions of the retro-stepped dielectric material portions is located at a second-tier level that overlies the first-tier level, and comprises a respective pair of bottommost surfaces contacting a respective lengthwise sidewall of the first backside trench fill structure.
Conclusion
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/CARNELL HUNTER III/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893