DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-6, 10-13, 15-16, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YOON et al. (US 20220181457 A1, hereinafter Yoon)
With regards to claim 1, Yoon discloses a semiconductor memory device, (FIGS. 1-17) comprising:
a substrate (substrate 100) including a first source/drain region (source 130a) and a second source/drain region; (drain 130b)
a trench (recess 104) in the substrate between the first source/drain region and the second source/drain region; (See FIG. 17)
a cell gate insulating layer (gate insulation layer 106) on at least a portion of sidewalls and a bottom surface of the trench;
a cell gate electrode (metal 112a) on at least a portion of the cell gate insulating layer;
a work function control pattern (layers 116, 118, and 120a) on the cell gate electrode, the work function control pattern including N-type impurities; and
a cell gate capping pattern (cap 122) on the work function control pattern,
wherein;
the work function control pattern includes a first region (region including 99% of barrier 118 and pattern 120a, see annotated FIG. 2) and a second region (“L-shaped” region, which includes pattern 116 and 1% of barrier 118 and pattern 120a, see annotated FIG. 1)) between the first region and the cell gate electrode,
each of the first region and the second region includes a semiconductor material, (polysilicon of layer 120a, where 99% of layer 120a is in the first region, and where 1% of layer 120a is in the second region) and
a concentration of the N-type impurities in the first region is greater than that of the N- type impurities in the second region. (Paragraph [0042]: “A concentration of the nitrogen included in the upper barrier interface layer pattern 118 may be higher/greater than a concentration of the nitrogen included in the barrier interface layer pattern 116, e.g. greater by several orders of magnitude.” See FIGS. 2 and 17, where the concentration of nitrogen in the first region (which comprises 99% of layer 118) would be higher than the concentration of nitrogen in the second region (which comprises 1% of layer 118), see also Response to Arguments)
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With regards to claim 2, Yoon discloses the semiconductor memory device of claim 1, wherein a concentration of the N-type impurities in the work function control pattern is reduced as the work function control pattern becomes farther away from the cell gate capping pattern. (Paragraph [0042]: “A concentration of the nitrogen included in the upper barrier interface layer pattern 118 may be higher/greater than a concentration of the nitrogen included in the barrier interface layer pattern 116, e.g. greater by several orders of magnitude.” Thus, the concentration is reduced from a distance from the cap 122)
With regards to claim 3, Yoon discloses the semiconductor memory device of claim 1, wherein the concentration of the N-type impurities in the first region is increased and then decreased as the first region becomes farther away from the gate capping pattern. (Paragraph [0042]-[0046]: “A concentration of the nitrogen included in the upper barrier interface layer pattern 118 may be higher/greater than a concentration of the nitrogen included in the barrier interface layer pattern 116, e.g. greater by several orders of magnitude…In some example embodiments, the second gate pattern 120a may include a semiconductor material doped with N-type impurities such as at least one of arsenic or phosphorus, or P-type impurities such as boron.” Thus, the concentration of nitrogen increases then decreases away from the cap)
With regards to claim 5, Yoon discloses the semiconductor memory device of claim 1, wherein the N-type impurities type include phosphorus. (Paragraph [0046]: “In some example embodiments, the second gate pattern 120a may include a semiconductor material doped with N-type impurities such as at least one of arsenic or phosphorus, or P-type impurities such as boron.”)
With regards to claim 6, Yoon discloses the semiconductor memory device of claim 1, wherein the second region further includes P-type impurities. (Paragraph [0046]: “In some example embodiments, the second gate pattern 120a may include a semiconductor material doped with N-type impurities such as at least one of arsenic or phosphorus, or P-type impurities such as boron.”)
With regards to claim 10, Yoon discloses the semiconductor memory device of claim 1, further comprising a barrier layer (barrier metal 110a) between the cell gate electrode and the work function control pattern. (See FIG. 16)
With regards to claim 11, Yoon discloses the semiconductor memory device of claim 1, wherein a work function of the first region is smaller than a work function of the second region, and the work function of the second region is smaller than a work function of the cell gate electrode. (Paragraphs [0040]-[0048]: “the barrier interface layer pattern 116 may include at least one of tungsten nitride (WNx) and tungsten oxynitride (WxOyNz)…For example, the metal pattern 112a may include tungsten, and in this case, the first work function may be about 4.58 eV…the second gate pattern 120a may have a second work function different from the first work function. The second work function may be lower than/less than the first work function.”)
With regards to claim 12, Yoon discloses a semiconductor memory device, (FIGS. 1-17) comprising:
a substrate (substrate 100) including an active region (active region 130) defined by an element isolation layer; (dielectric 142)
a bit line (bit line 430) extending in a first direction on the substrate;
an information storage element (capacitor 442) at opposing sides of the bit line and connected to the active region; and
a cell gate structure (gate 114) extending in a second direction crossing the first direction in the substrate, wherein the cell gate structure includes:
a trench (trench 104) in the substrate;
a cell gate insulating layer (insulation layer 106) on at least a portion of sidewalls and a bottom surface of the trench;
a cell gate electrode (metal 112a) on at least a portion of the cell gate insulating layer;
a barrier layer (barrier 110a) on at least a portion of the cell gate electrode; and
a work function control pattern (layers 116, 118, and 120a) on the barrier layer, wherein the work function control pattern includes a first region (region including 99% of barrier 118 and pattern 120a, see annotated FIG. 2) including N-type impurities, (nitrogen in layer 118) and
a second region and a second region (“L-shaped” region, which includes pattern 116 and 1% of barrier 118 and pattern 120a, see annotated FIG. 2)) between the first region and the cell gate electrode, (see FIG. 17)
each of the first region and the second region includes a semiconductor material, (polysilicon of layer 120a, where 99% of layer 120a is in the first region, and where 1% of layer 120a is in the second region, see also Response to Arguments) and
With regards to claim 13, Yoon discloses the semiconductor memory device of claim 12, wherein a concentration of the N- type impurities in the first region is greater than a concentration of the N-type impurities in the second region. (Paragraph [0042]: “A concentration of the nitrogen included in the upper barrier interface layer pattern 118 may be higher/greater than a concentration of the nitrogen included in the barrier interface layer pattern 116, e.g. greater by several orders of magnitude.” See FIGS. 1 and 17, where the concentration of nitrogen in the first region (which comprises 99% of layer 118) would be higher than the concentration of nitrogen in the second region (which comprises 1% of layer 118), see also Response to Arguments)
With regards to claim 15, Yoon discloses the semiconductor memory device of claim 12, wherein the second region includes P-type impurities. (Paragraph [0046]: “In some example embodiments, the second gate pattern 120a may include a semiconductor material doped with N-type impurities such as at least one of arsenic or phosphorus, or P-type impurities such as boron.”)
With regards to claim 16, Yoon discloses the semiconductor memory device of claim 12, wherein a work function of the second region is smaller than a work function of the cell gate electrode. (Paragraphs [0040]-[0048]: “the barrier interface layer pattern 116 may include at least one of tungsten nitride (WNx) and tungsten oxynitride (WxOyNz)…For example, the metal pattern 112a may include tungsten, and in this case, the first work function may be about 4.58 eV…the second gate pattern 120a may have a second work function different from the first work function. The second work function may be lower than/less than the first work function.”)
With regards to claim 18, Yoon discloses a semiconductor memory device, (FIGS. 1-17) comprising:
a substrate (substrate 100) including an active region (active region 130) defined by an element isolation layer (isolation region 142) and extending in a first direction, the active region including a first portion and a second portion at opposing sides of the first portion; (130a,130b)
a cell gate structure (gate 114) extending in a second direction in the substrate and the element isolation layer, crossing between the first portion of the active region and the second portion of the active region;
a bit line (bit line 430) extending in a third direction on the substrate and the element isolation layer and connected to the first portion of the active region;
a storage contact (contact 440) at opposing sides of the bit line and connected to the second portion of the active region;
a storage pad (pad 442a) connected to the storage contact on the storage contact; and
a capacitor (capacitor 442) connected to the storage pad on the storage pad, wherein the cell gate structure includes:
a trench (trench 104) in the substrate;
a cell gate insulating layer (insulation layer 106) on at least a portion of sidewalls and a bottom surface of the trench;
a cell gate electrode (electrode 112a) on at least a portion of the cell gate insulating layer;
a work function control pattern on at least a portion of the cell gate electrode, the work function control pattern including N-type impurities;
a cell gate capping pattern (layers 116, 118, and 120a) on at least a portion of the work function control pattern,
the work function control pattern includes a first region (region including 99% of barrier 118 and pattern 120a, see annotated FIG. 2) and a second region (“L-shaped” region, which includes pattern 116 and 1% of barrier 118 and pattern 120a, see annotated FIG. 2)) between the first region and the cell gate electrode,
each of the first region and the second region includes a semiconductor material, (polysilicon of layer 120a, where 99% of layer 120a is in the first region, and where 1% of layer 120a is in the second region, see also Response to Arguments)
a concentration of the N-type impurities in the first region is greater than a concentration of the N-type impurities in the second region. (Paragraph [0042]: “A concentration of the nitrogen included in the upper barrier interface layer pattern 118 may be higher/greater than a concentration of the nitrogen included in the barrier interface layer pattern 116, e.g. greater by several orders of magnitude.” See FIGS. 2 and 17, where the concentration of nitrogen in the first region (which comprises 99% of layer 118) would be higher than the concentration of nitrogen in the second region (which comprises 1% of layer 118), see also Response to Arguments)
Allowable Subject Matter
Claims 4, 7-9, 14, 17, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 03/30/2026 have been fully considered but they are not persuasive.
Examiner notes that the term “region” is incredibly broad, and Examiner can draw imaginary boundaries to represent each region. Thus, based on the annotated FIG. 1 shown above, the second region now includes a small sliver of the semiconductor of layer 120a while still meeting the criteria of having less concentration of nitrogen, as required in claims 1, 12, and 18.
Therefore, claims 1, 12, and 18 are properly rejected, and claims 2-3, 5-6, 10-11, 13, and 15-16 are rejected for at least their dependencies.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
TSAI (US 20240015951 A1) – different work functions in a trench gate.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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