DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 3/5/26 have been fully considered but they are not persuasive.
After reviewing the remarks on 3/5/26, and the applicant argues that Applicant respectfully asserts that IWAMOTO is silent to any operation of the test module 14 that includes measuring currents and/or voltages of a device with respect to time, determining matching criteria for the device based on transfer data, or outputting binning and/or matching criteria for the device.
IWAMOTO does not teach nor fairly disclose a "device binning and/or matching process comprising: measuring with a testing device currents and/or voltages of a device with respect to time; determining with the testing device binning and/or matching criteria for the device based on transfer data generated from the device currents and/or the voltages measured with respect to time; and outputting with the testing device the binning and/or matching criteria for the device" as recited by claim 1.”
However, Iwamoto disclose [0019] FIG. 1 shows a configuration of a test apparatus 10 according to an embodiment of the present invention with a DUT 100. The test apparatus 10 tests the DUT (Device Under Test) 100. More specifically, the test apparatus 10 generates a test signal, provides the same to the DUT 100 and determines pass/fail of the DUT 100 based on whether an output signal outputted from the DUT 100 as the result that the DUT 100 operates based on the test signal is matched with an expected value; [0023] The measuring instrument 16 measures a reference parameter including at least one of the reference voltage, the reference resistance and the reference current. The measuring instrument 16 receives from a command from the control device 20 and measures according to the received command. Then, the measuring instrument 16 returns the measurement result to the control device 20; A test apparatus that tests a device under test is provided. The test apparatus includes a test module that provides a test signal to the device under test. The test apparatus includes: a test module that provides a test signal to the device under test; a measuring instrument that measures a reference parameter including at least one of a reference voltage, a reference resistance and a reference current included in the test module; and a control device that controls the test module and the measuring instrument. By executing a diagnostic program that diagnose the plurality of test modules by using the measuring instruments, the control device to function as: a target diagnostic section that diagnoses a target test module; an acquirement section that acquires measuring instrument identification information indicative of the kind of the measuring instrument provided in the test apparatus; a measurement processing section provided for each kind of the measuring instruments and executed on the control device that issues a command to cause the measuring instrument to measure the value of the reference parameter of the test module to the measuring instrument and receives a measurement result of the reference parameter from the measuring instrument; and a switching section that calls the measurement processing section corresponding to the measuring instrument identified by the measuring instrument identification information in response to receiving the call to instruct to measure the value of a reference parameter included in the test module, executes the same and returns the measurement result of the reference parameter to the target diagnostic section. (abstract)
Therefore, Iwamoto discloses the limitations of claim 1 as claim recite also in the rejection below.
Furthermore, COLE does not teach nor fairly disclose a "process of configuring a power module, comprising: providing at least one power substrate; arranging a housing on the at least one power substrate; selecting a plurality of power devices based on at least transfer data of the plurality of power devices; and electrically connecting the plurality of power devices to the at least one power substrate" as recited by claim 17.
However, Cole discloses (19) FIG. 3 shows details of power converter circuitry 32 within the housing 12 according to one embodiment of the present disclosure. The power converter circuitry 32 includes a number of power semiconductor die 34, a number of interconnect printed circuit boards (PCBs) 36, and a number of removable jumpers 38 coupled between the interconnect PCBs 36. Each one of the power semiconductor die 34 are mounted to a power substrate 40 and include a number of contact pads 42 on the top side thereof for electrically connecting to the power semiconductor die 34. Wire bonds 44 connect the various contact pads 42 of each power semiconductor die 34 to a desired connection point. In one embodiment, each one of the power semiconductor die 34 is a metal-oxide-semiconductor field-effect transistor (MOSFET) such that the contact pads 42 include a gate contact, a drain contact, and a source contact (not shown). In other embodiments, each one of the power semiconductor die 34 may be an insulated gate bipolar transistor (IGBT). The drain contact and the source contact of each one of the power semiconductor die 34 are coupled to one of the bolted connectors 28A, which extend through the lid as discussed above and provide the connection points for the high voltage and/or high current switching path provided by the power semiconductor die 34. The gate contact and the source contact of each one of the power semiconductor die 34 are coupled to one of the low-noise connectors 28B via one of the interconnect PCBs 36. Specifically, the gate contact of each one of the power semiconductor die 34 is coupled to a first connection point in one of the low-noise connectors 28B, while the source contact of each one of the power semiconductor die 34 is coupled to a second connection point of the same one of the low-noise connectors 28B, which is isolated from the first connection point. The low-noise connectors 28B provide the connection points for low voltage and/or low current control signals to be provided to the power semiconductor die 34.
(20) The power semiconductor die 34 may be arranged in groups 46 as further illustrated in FIG. 4. Each group 46 may include six power semiconductor die 34 coupled in series in order to distribute a voltage provided across the group 46 and therefore increase the voltage handling capability thereof. Each group 46 may be paired with another group to form a sub-module 48. Each paired group 46 may similarly be connected in series such that each sub-module 48 includes twelve power semiconductor die 34 coupled in series. Accordingly, a first row of the bolted connectors 28A may provide a connection to a drain of a first one of the power semiconductor die 34 in a respective sub-module 48, a second row of the bolted connectors 28A may provide a connection to drain-source connection between a first group 46 and a second group 46 in a respective sub-module 48, and a third row of the bolted connectors 28A may provide a connection to a source connection of a last one of the power semiconductor die 34 in a respective sub-module 48. The gate-source control connections for each power semiconductor die 34 in the respective groups 46 may be coupled together via a respective interconnect PCB 36. The gate-source connections between various ones of the groups 46 may be coupled together by the removable jumpers 38. While not shown, a gate return or source sense connection is generally provided to each one of the source connections of the power semiconductor die 34, and a desaturation connection is generally provided to protect against severe low impedance short circuits.
Therefore, Cole discloses the limitations of claim 17 as claim recite also in the rejection below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 7-12, 15-16 is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Iwamoto (2008/0129313 hereinafter Iwamoto).
As to claim 1, Iwamoto discloses in Figs. 1, a device binning and/or matching process comprising:
measuring with a testing device (16-1-16-n as shown in Fig. 1) currents and/or voltages of a device with respect to time (paras 0021-0022);
determining ( via 14-1-14-n as shown in Fig. 1) with the testing device binning and/or matching criteria for the device based on transfer data generated from the device currents and/or the voltages measured with respect to time (paras 0021-0022); and
outputting with the testing device the binning and/or matching criteria for the device (para 0019).
As to claim 2, Iwamoto discloses in Figs. 1, further comprising applying with a testing device voltages and/or currents to a device (paras 0021-0022),
wherein the applying the voltages and/or the currents to the device comprises applying a gate voltage (paras 0022).
As to claim 3, Iwamoto discloses in Figs. 1, wherein the measuring the currents and/or voltages with respect to time comprises measuring a turn-on drain current of the device with respect to time (para 0024).
As to claim 4, Iwamoto discloses in Figs. 1, wherein the measuring the currents and/or voltages with respect to time comprises measuring a gate-source voltage with respect to time (para 0024).
As to claim 7, Iwamoto discloses in Figs. 1, wherein the determining binning and/or matching criteria based on the transfer function comprises a current range (paras 0024-0026).
As to claim 8, Iwamoto discloses in Fig. 1, wherein the determining binning and/or matching criteria further comprises determining secondary device characterization values;
wherein the secondary device characterization values include at least one of the following: an anticipated implementation location of the device, an anticipated implementation temperature of the device, an anticipated implementation configuration of the device, an anticipated implementation voltage of the device, an anticipated implementation current of the device, an anticipated
implementation environment of the device, an anticipated implementation humidity of the device, an anticipated number of the devices implemented, an anticipated implementation location of the device, and an anticipated implementation position of the device (paras 0024-0026; and wherein the determining binning and/or matching criteria is based on the transfer function and the secondary device characterization values (para 0024-0026).
As to claim 9, Iwamoto discloses in Figs. 1, A system configured for device binning and/or matching comprising:
at least one testing device (16-1-16-n as shown in Fig. 1) configured to measure currents and/or voltages of a device (100 as shown in Fig. 1) with respect to time (paras 0021-0022);
the at least one testing device configured to determine binning and/or matching criteria (14-1-14-n as shown in Fig. 1) for the device based on transfer data generated from the device currents and/or the voltages measured with respect to time (paras 0021-0022); and
the at least one testing device configured to output the binning and/or matching criteria for the device based on the transfer data (para 0019).
As to claim 10, Iwamoto discloses in Fig. 1, wherein an application of the voltages and/or the currents to the device comprises application of a gate voltage (paras 0022).
As to claim 11, Iwamoto discloses in Fig. 1, wherein a measurement of the currents and/or the voltages with respect to time comprises a measurement of a turn-on drain current of the device with respect to time (para 0024).
As to claim 12, Iwamoto discloses in Fig. 1, wherein a measurement of the currents and/or the voltages with respect to time comprises a measurement of a gate-source voltage with respect to time (para 0024).
As to claim 15, Iwamoto discloses in Fig. 1, wherein a determination of the binning and/or matching criteria based on the transfer data comprises a current range (paras 0024-0026).
As to claim 16, Iwamoto discloses in Fig. 1, wherein the determining binning and/or matching criteria further comprises determining secondary device characterization values;
wherein the secondary device characterization values include at least one of the following: an anticipated implementation location of the device, an anticipated implementation temperature of the device, an anticipated implementation configuration of the device, an anticipated implementation voltage of the device, an anticipated implementation current of the device, an anticipated
implementation environment of the device, an anticipated implementation humidity of the device, an anticipated number of the devices implemented, an anticipated implementation location of the device, and an anticipated implementation position of the device (para 0024-0026); and wherein the determining binning and/or matching criteria is based on the transfer function and the secondary device characterization values (para 0024-0026).
Claim(s) 17 is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Cole et al. (US 9,839,146 hereinafter Cole).
As to claim 17, Cole discloses in Figs. 1-5, a process of configuring a power module (10 as shown in Fig. 5), comprising: providing at least one power substrate (40 as shown in Fig. 5); arranging a housing (50 as shown in Fig. 5) on the at least one power substrate (40 as shown in Fig. 5); selecting a plurality of power devices (34 as shown in Fig. 4) based on at least transfer data of the plurality of power devices (34 as shown in Fig. 4, and also col. 3, lines 5-15); and electrically connecting the plurality of power devices to the at least one power substrate (as shown in Figs. 3-5).
Allowable Subject Matter
Claims 5-6, 13-14, 18-25 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claims 5-6, 13, 14, the prior art does not disclose wherein the measuring the currents and/or the voltages with respect to time comprises measuring a turn-on drain current of the device with respect to time and a gate-source voltage with respect to time, as recited in claims 5, 13; wherein the transfer data comprises at least one of the following: a device transfer curve, a transfer function, and data representative of an independent scalar input versus a dependent scalar output, as recited in claims 6, 14; sweeping or varying application of voltages and/or currents to each of the plurality of power devices; generating the transfer data based on the currents and/or the voltages with respect to time of each of the plurality of power devices; selecting and comparing at least one operating point of the transfer data of the plurality of power devices; as recited in claims 18-25.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUNG X NGUYEN whose telephone number is (571)272-1967. The examiner can normally be reached 10:30am-6:30pm M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at 571-272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUNG X NGUYEN/Primary Examiner, Art Unit 2858 5/15/26
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