DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-11 in the reply filed on 11/06/25 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schrock (USPGPUB DOCUMENT: 20180012865, hereinafter Schrock) in view of Tsao (USPGPUB DOCUMENT: 2021/0202358, hereinafter Tsao).
Re claim 1 Schrock discloses in Fig 3 an integrated circuit device package comprising: a package structure having a base(102) and walls(left/right 115a) extending from the base(102); at least one integrated circuit die(104/106) mounted to the package structure base(102) within the walls(left/right 115a), each integrated circuit die(104/106) among the at least one integrated circuit die(104/106) having a top surface parallel to the base(102) and each integrated circuit die(104/106) among the at least one integrated circuit die(104/106) having a thickness extending along an axis, perpendicular to the top surface, at most equal to a height of the walls(left/right 115a); a thermally conductive heat spreader(316) extending parallel to the base(102) above the at least one integrated circuit die(104/106) and above the walls(left/right 115a); and an interface layer(120) comprising: an adhesive layer portion(left/right 120 portions)[0036] disposed between the walls(left/right 115a) and the heat spreader(316) to adhere the heat spreader to the walls(left/right 115a); and a thermal interface material (TIM) layer portion(middle 120 portion)[0020,0036] coplanar with, and laterally displaced from, the adhesive layer portion(left/right 120 portions)[0036], to dissipate heat from each respective integrated circuit die(104/106) to the heat spreader(316).
Schrock does not disclose the TIM layer portion being disposed in thermally conductive relationship between the heat spreader and each respective integrated circuit die(104/106) from among the at least one integrated circuit die(104/106),
Tsao discloses the TIM layer portion(250/260)[0040 of Tsao]
It would have been obvious to one of ordinary skill in the art at the time of the inventions to use the material of Tsao to replace the material (underfill 110) of Schrock’s device because such material replacement is art recognized suitability for an intended purpose. See MPEP 2144.07. In doing so, the TIM layer portion(250/260)[0040 of Tsao] being disposed in thermally conductive relationship between the heat spreader(316) and each respective integrated circuit die(104/106) from among the at least one integrated circuit die(104/106),
Re claim 2 Schrock and Tsao disclose the integrated circuit device package of claim 1, wherein the package structure comprises molded[0019] packaging material.
Re claim 3 Schrock and Tsao disclose the integrated circuit device package of claim 1, wherein the adhesive layer portion(left/right 120 portions)[0036] is thermally conductive.
Re claim 4 Schrock and Tsao disclose the integrated circuit device package of claim 1, wherein dies from among the at least one integrated circuit die(104/106) are arranged in a stack of integrated circuit die(104/106)s, the stack having a stack thickness, perpendicular to the top surface, at most equal to the height of the walls(left/right 115a).
Re claim 5 Schrock and Tsao disclose the integrated circuit device package of claim 1, wherein the TIM layer portion comprises any one of a: (a) polymer TIM, (b) graphite TIM, (c) metal TIM, and (d) liquid metal TIM.
Re claim 6 Schrock and Tsao disclose the integrated circuit device package of claim 1, wherein the adhesive layer portion(left/right 120 portions)[0036] surrounds the TIM layer portion in the interface layer(120).
Re claim 7 Schrock and Tsao disclose the integrated circuit device package of claim 1 wherein: the TIM layer portion is flowable; and the adhesive layer portion(left/right 120 portions)[0036] surrounds the TIM layer portion in the interface layer(120).
Re claim 8 Schrock and Tsao disclose the integrated circuit device package of claim 7 wherein the adhesive layer portion(left/right 120 portions)[0036] forms a barrier between the integrated circuit die(104/106) and the heat spreader(316), to contain the flowable TIM layer portion.
Re claim 9 Schrock and Tsao disclose the integrated circuit device package of claim 1, wherein the heat spreader(316) comprises a flat lid.
Re claim 10 Schrock and Tsao disclose the integrated circuit device package of claim 1, wherein the heat spreader(316) comprises a forged lid.
Re claim 11 Schrock and Tsao disclose the integrated circuit device package of claim 1, wherein the heat spreader(316) comprises a stamped hat-shaped lid.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812