Prosecution Insights
Last updated: October 02, 2026
Application No. 18/348,041

INTEGRATED CIRCUIT DEVICE EXPOSED DIE PACKAGE STRUCTURE WITH ADHESIVE

Final Rejection §103
Filed
Jul 06, 2023
Priority
Jul 07, 2022 — provisional 63/358,908
Examiner
VALENZUELA, PATRICIA D
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Marvell Asia Pte. Ltd.
OA Round
2 (Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
652 granted / 722 resolved
+22.3% vs TC avg
Minimal +2% lift
Without
With
+2.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
82 currently pending
Career history
804
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
68.2%
+28.2% vs TC avg
§102
15.8%
-24.2% vs TC avg
§112
6.2%
-33.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 722 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schrock (USPGPUB DOCUMENT: 20180012865, hereinafter Schrock) in view of Tsao (USPGPUB DOCUMENT: 2021/0202358, hereinafter Tsao) and Wang (USPGPUB DOCUMENT: 2023/0065147, hereinafter Wang). Re claim 1 Schrock discloses in Fig 3 an integrated circuit device package comprising: a package structure having a base(102) and walls(left/right 115a) extending from the base(102); at least one integrated circuit die(104/106) mounted to the package structure base(102) within the walls(left/right 115a), each integrated circuit die(104/106) among the at least one integrated circuit die(104/106) having a top surface parallel to the base(102) and each integrated circuit die(104/106) among the at least one integrated circuit die(104/106) having a thickness extending along an axis, perpendicular to the top surface, at most equal to a height of the walls(left/right 115a); a thermally conductive heat spreader(316) extending parallel to the base(102) above the at least one integrated circuit die(104/106) and above the walls(left/right 115a); and an interface layer(120) comprising: an adhesive layer portion(left/right 120 portions)[0036] disposed between the walls(left/right 115a) and the heat spreader(316) to adhere the heat spreader to the walls(left/right 115a); and a thermal interface material (TIM) layer portion(middle 120 portion)[0020,0036] coplanar with, and laterally displaced from, the adhesive layer portion(left/right 120 portions)[0036], to dissipate heat from each respective integrated circuit die(104/106) to the heat spreader(316). Schrock does not disclose the TIM layer portion being disposed in thermally conductive relationship between the heat spreader and each respective integrated circuit die(104/106) from among the at least one integrated circuit die(104/106); wherein the adhesive layer portion contacts opposite sides of the TIM layer portion to define a barrier containing the TIM layer portion between each integrated circuit die and the heat spreader. Tsao discloses the TIM layer portion(250/260)[0040 of Tsao] It would have been obvious to one of ordinary skill in the art at the time of the inventions to use the material of Tsao to replace the material (underfill 110) of Schrock’s device because such material replacement is art recognized suitability for an intended purpose. See MPEP 2144.07. In doing so, the TIM layer portion(250/260)[0040 of Tsao] being disposed in thermally conductive relationship between the heat spreader(316) and each respective integrated circuit die(104/106) from among the at least one integrated circuit die(104/106), Schrock and Tsao does not disclose wherein the adhesive layer portion contacts opposite sides of the TIM layer portion to define a barrier containing the TIM layer portion between each integrated circuit die and the heat spreader. Wang disclose wherein the adhesive layer portion(left/right 600) contacts opposite sides of the TIM layer portion(left/right 206) to define a barrier containing the TIM layer portion between each integrated circuit die(100) and the heat spreader(300)[0050]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Wang to the teachings of Schrock in order to increase production efficiency, lower costs, and/or improving performance [0001, Wang]. Re claim 2 Schrock and Tsao and Wang disclose the integrated circuit device package of claim 1, wherein the package structure comprises molded[0019] packaging material. Re claim 3 Schrock and Tsao and Wang disclose the integrated circuit device package of claim 1, wherein the adhesive layer portion(left/right 120 portions)[0036] is thermally conductive. Re claim 4 Schrock and Tsao and Wang disclose the integrated circuit device package of claim 1, wherein dies from among the at least one integrated circuit die(104/106) are arranged in a stack of integrated circuit die(104/106)s, the stack having a stack thickness, perpendicular to the top surface, at most equal to the height of the walls(left/right 115a). Re claim 5 Schrock and Tsao and Wang disclose the integrated circuit device package of claim 1, wherein the TIM layer portion comprises any one of a: (a) polymer TIM, (b) graphite TIM, (c) metal TIM, and (d) liquid metal TIM. Re claim 6 Schrock and Tsao and Wang disclose the integrated circuit device package of claim 1, wherein the adhesive layer portion(left/right 120 portions)[0036] surrounds the TIM layer portion in the interface layer(120). Re claim 7 Schrock and Tsao and Wang disclose the integrated circuit device package of claim 1 wherein: the TIM layer portion is flowable; and the adhesive layer portion(left/right 120 portions)[0036] surrounds the TIM layer portion in the interface layer(120). Re claim 8 Schrock and Tsao and Wang disclose the integrated circuit device package of claim 7 wherein the adhesive layer portion(left/right 120 portions)[0036] is configured to form the barrier between the integrated circuit die(104/106) and the heat spreader(316), to contain the flowable TIM layer portion. Re claim 9 Schrock and Tsao and Wang disclose the integrated circuit device package of claim 1, wherein the heat spreader(316) comprises a flat lid. Re claim 10 Schrock and Tsao and Wang disclose the integrated circuit device package of claim 1, wherein the heat spreader(316) comprises a forged lid. Re claim 11 Schrock and Tsao and Wang disclose the integrated circuit device package of claim 1, wherein the heat spreader(316) comprises a stamped hat-shaped lid. Response to Arguments Applicant’s arguments with respect to claim(s) 1-11 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jul 06, 2023
Application Filed
Feb 25, 2026
Non-Final Rejection mailed — §103
Jun 25, 2026
Response Filed
Sep 09, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12721165
SEMICONDUCTOR CIRCUIT STRUCTURE WITH DIRECT DIE HEAT REMOVAL STRUCTURE
1y 0m to grant Granted Aug 25, 2026
Patent 12708031
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREFOR
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Patent 12702000
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Patent 12701980
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+2.0%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 722 resolved cases by this examiner. Grant probability derived from career allowance rate.

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