Prosecution Insights
Last updated: October 02, 2026
Application No. 18/348,211

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Jul 06, 2023
Priority
Mar 07, 2023 — RE 10-2023-0030162
Examiner
AU, BAC H
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
3 (Non-Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
684 granted / 845 resolved
+12.9% vs TC avg
Moderate +11% lift
Without
With
+11.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
18 currently pending
Career history
867
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
50.9%
+10.9% vs TC avg
§102
27.9%
-12.1% vs TC avg
§112
12.3%
-27.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 845 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 2, 2026, has been entered. Response to Amendment Applicant’s amendment dated June 7, 2026, in which claims 1, 6-8, 10, 12 and 17-19 were amended, has been entered. Claim Objections Claim 1 is objected to because of the following informalities: It appears the term “and” is missing in the limitation “…the first wiring part (and) the first via part are connected…” in lines 7-8. Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-8 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. Pub. 2022/0262738) [Hereafter “Lee”] in view of Ting et al. (U.S. Pub. 2014/0264873) [Hereafter “Ting”] and Kang (U.S. Pub. 2014/0210087). Regarding claim 1, Lee [Fig.2] discloses a semiconductor device comprising: a first interconnection structure [314]; and a second interconnection structure including a first wiring part [324/325] electrically connected to the first interconnection structure [314], a first hard mask pattern [327] on the first wiring part, and a first via part [V21] connected to the first wiring part through the first hard mask pattern. Lee fails to explicitly disclose wherein the first wiring part and the first via part are connected as a single layer. However, Ting [Figs.8B,9B] discloses a semiconductor device wherein the first wiring part [trench portion of interconnect structure 416] and the first via part [via portion of interconnect structure 416] are connected as a single layer. It would have been obvious to provide wherein the first wiring part and the first via part are connected as a single layer, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Lee fails to explicitly disclose wherein the first wiring part is wider than the first interconnection structure at a connection where the first wiring part and the first interconnection structure are connected. However, Kang [Fig.25] discloses a semiconductor device wherein the first wiring part [142] is wider than the first interconnection structure [BC] at a connection where the first wiring part and the first interconnection structure are connected. It would have been obvious to provide wherein the first wiring part is wider than the first interconnection structure at a connection where the first wiring part and the first interconnection structure are connected, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Regarding claims 2-5, 8, and 17, Lee [Fig.2] discloses a semiconductor device comprising: wherein the second interconnection structure comprises: a barrier layer [322]; and a metal layer located in the barrier layer and including the first wiring part [324/325] and the first via part [334/V21]; wherein the barrier layer includes metal nitride [Para.62] and the metal layer includes tungsten (W) [Para.65]; wherein the second interconnection structure includes a metal layer including the first wiring part [324/325] contacting the first hard mask pattern [327] and the first via part [V21]; wherein the metal layer includes molybdenum (Mo) [Para.65]; further comprising a substrate [100/311]; wherein a first direction is parallel to a surface of the substrate, and a second direction is orthogonal to the surface of the substrate; wherein the first wiring part [324/325] has a first width in the first direction and a first height in the second direction, the first via part [V21] has a second width in the first direction at a connection where the first wiring part and the first via part are connected, and a magnitude of the first width and a magnitude of the first height are greater than a magnitude of the second width [Fig.2]; further comprising a circuit [100,200] electrically connected to the first interconnection structure [300] [Fig.1]. Regarding claim 6, Lee [Fig.2] substantially discloses a semiconductor device, further comprising a substrate; wherein a first direction is parallel to a surface of the substrate, and a second direction is orthogonal to the surface of the substrate; wherein the first wiring part has a first width in the first direction and a first height in the second direction, the first via part has a second width in the first direction at a connection where the first wiring part and the first via part are connected. Lee fails to explicitly disclose wherein a magnitude of the second width is greater than a magnitude of the first height. However, Ting [Figs.7-9] discloses and makes obvious various relative shapes and sizes of the first wiring part [trench portion of interconnect structure 416] and the first via part [via portion of interconnect structure 416]. Ting [Fig.7D] discloses a magnitude of the second width [at connection region] is greater than a magnitude of the first height [h1]. It would have been obvious to use provide wherein a magnitude of the second width is greater than a magnitude of the first height, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Regarding claim 7, Lee discloses wherein the first wiring part has a first width and a first height, the first via part has a second width. Lee fails to explicitly disclose the second width at a connection where the first wiring part and the first via part are connected, and the second width is greater than the first width. However, Ting [Fig.9B] discloses a semiconductor device wherein the second width at a connection where the first wiring part [414/416] and the first via part [714] are connected, and the second width is greater than the first width [Fig.9B]. It would have been obvious to provide the relative widths as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. Pub. 2022/0262738) [Hereafter “Lee”] in view of Ting et al. (U.S. Pub. 2014/0264873) [Hereafter “Ting”] and Kang (U.S. Pub. 2014/0210087), as applied above and further in view of Tseng et al. (U.S. Pub. 2022/0336269) [Hereafter “Tseng”]. Regarding claim 9, Lee fails to explicitly disclose wherein the first wiring part includes a void. However, Tseng [Fig.11] discloses a semiconductor device wherein the first wiring part [238] includes a void [2380]. Tseng [Para.27] discloses and makes obvious various deposition processes may form voids in the interconnect structure. It would have been obvious to provide wherein the first wiring part includes a void, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Allowable Subject Matter Claims 10-16 and 18-20 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Applicant’s amendments to the claims and/or arguments were persuasive. Additional reasons for allowance were provided in the previous Office Action. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Response to Arguments Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Overall, Applicant’s arguments are not persuasive and the rejected claims stand rejected. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art is considered analogous art and discloses at least some of the claimed subject matter of the current invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BAC H AU whose telephone number is (571)272-8795. The examiner can normally be reached M-F 9:00AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BAC H AU/Primary Examiner, Art Unit 2898
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Prosecution Timeline

Jul 06, 2023
Application Filed
Oct 01, 2025
Non-Final Rejection mailed — §103
Dec 29, 2025
Response Filed
Apr 06, 2026
Final Rejection mailed — §103
Jun 07, 2026
Response after Non-Final Action
Jul 02, 2026
Request for Continued Examination
Jul 08, 2026
Response after Non-Final Action
Sep 10, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
92%
With Interview (+11.0%)
2y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 845 resolved cases by this examiner. Grant probability derived from career allowance rate.

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