DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I (Fig. 1-5, 12, claims 1-8, 14-18 and 20) in the reply filed on 10/27/2025 is acknowledged.
Claims 9-13 and 19 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/27/2025.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/06/2023 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 14 is objected to because of the following informalities:
Claim 14 line 13, after “wherein” delete “the” . Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 14 and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung et al. (US 2020/0312826).
As for claim 14, Jung et al. disclose in Figs. 1-2B and the related text a semiconductor package, comprising:
a package substrate 100 that includes first (lower) and second (upper) surfaces that are opposite to each other (fig. 1);
first connecting terminals 105 disposed on the first surface of the package substrate (fig. 1);
an interposer 200 disposed on the second surface of the package substrate (fig. 1), wherein the interposer 200 includes a third (lower) surface that faces the second surface and a fourth (upper) surface that is opposite to the third surface (fig. 1);
(1-1)-th connecting pads (some of 214a) and (1-2)-th connecting pads (others of 214a) disposed on the third surface of the interposer (fig. 1-2B), wherein the (1-2)-th connecting pads have a smaller maximum width than the (1-1)-th connecting pads (fig. 2A-2B);
second connecting terminals 205 disposed between the (1-1)-th connecting pads, the (1-2)-th connecting pads, and the package substrate (fig. 1-2B);
(2-1)-th connecting pads (some of 305) and (2-2)-th connecting pads (others of 305) disposed on the fourth surface of the interposer (fig. 1), wherein the the (2-1)-th connecting pads and the (2-2)-th connecting pads have a same maximum width (Fig. 1);
a semiconductor chip 400/500 disposed on the fourth surface of the interposer (fig. 1); and
third connecting terminals 405/505 disposed between the (2-1)-th connecting pads, the (2-2)-th connecting pads, and the semiconductor chip (Fig. 1-2B),
wherein the (1-1)-th connecting pads and the (2-1)-th connecting pads transmit first signals, ground signals, or power signals (Fig. 1 teaches conductive pads as claimed and shows separate two conductive paths which connect the connecting pads, therefore it is capable to provide the connecting pads transmit first signals, ground signals, or power signals), and the (1-2)-th connecting pads and the (2-2)-th connecting pads transmit second signals, which are faster than the first signals.
The limitation “transmit first signals, ground signals, or power signals” has not been given patentable weight because it is considered to be functional language. This type of description does not affect the structure of the final device. It is respectfully noted that other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In a claim drawn to a process of making, the intended use must result in a manipulative difference as compared to the prior art. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). Note that Applicant has burden of proof in such cases, as the above case law makes clear. Furthermore, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Also, the limitation “a second signal that are faster than the first signals” is drawn to an operation of the device. Jung et al. the (1-1)-th connecting pads and the (2-1)-th connecting pads comprise conductive materials and have the same structure as claimed invention; therefore, it is capable to have transmit first signals, ground signals, or power signals and a second signal that are faster than the first signals.
As for claim 16, Jung et al. disclose the semiconductor package of claim 14, further comprising: first chip pads (upper portion of some of 405/505) and second chip pads (upper portion of others of 405/505) disposed on the semiconductor chip, wherein the first chip pads and the second chip pads have a same width (fig. 1-2B), wherein the third connecting terminals (lower portion of 405/505) are disposed on the first chip pads and the second chip pads (fig. 1), the first chip pads transmit the first signals, the ground signals, or the power signals, and the second chip pads transmit the second signals (Fig. 1 teaches conductive pads as claimed and shows separate two conductive paths which connect the conductive pads, therefore it is capable to have the substrate pads transmit the first and second signals, also see [0074]).
The limitation “transmit first signals, ground signals, or power signals” has not been given patentable weight because it is considered to be functional language. This type of description does not affect the structure of the final device. It is respectfully noted that other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In a claim drawn to a process of making, the intended use must result in a manipulative difference as compared to the prior art. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). Note that Applicant has burden of proof in such cases, as the above case law makes clear. Furthermore, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 15, 17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 2020/0312826).
As for claims 1-2, Jung et al. disclose in Figs. 1-2B and the related text a semiconductor package, comprising:
a package substrate 100 that includes first (lower) and second (upper) surfaces that are opposite to each other;
(1-1)-th substrate pads (some of terminal pads, [0025]) and (1-2)-th substrate pads (others of terminal pads, [0025]) disposed on the first surface of the package substrate;
first connecting terminals 105 disposed on the (1-1)-th substrate pads and the (1-2)-th substrate pads (Fig. 1);
(2-1)-th substrate pads (some of substrate pads, [0031]) and (2-2)-th substrate pads (others of substrate pads, [0031]) disposed on the second surface of the package substrate (Fig. 1);
an interposer 200 disposed on the second surface of the package substrate 100 (Fig. 1);
second connecting terminals 205 disposed between the (2-1)-th substrate pads, the (2-2)-th substrate pads, and the interposer (Fig. 1); and
a first semiconductor chip 400/500 disposed on the interposer,
wherein the (1-1)-th substrate pads and the (2-1)-th substrate pads transmit first signals, ground signals, or power signals and the (1-2)-th substrate pads and the (2-2)-th substrate pads transmit second signals (Fig. 1 teaches conductive pads as claimed and shows separate two conductive paths which connect the conductive pads, therefore it is capable to have the substrate pads transmit the first and second signals, also see [0074]), and
wherein the first connecting terminals include (1-1)-th connecting terminals (some of 105) disposed on the (1-1)-th substrate pads, (1-2)-th connecting terminals (others of 105) disposed on the (1-2)-th substrate pads.
Jung et al. do not disclose the (1-2)-th substrate pads have a smaller maximum width than the (1-1)-th substrate pads and wherein the (2-2)-th substrate pads have a smaller maximum width than the (2-1)-th substrate pads, and a maximum width of the (1-2)-th connecting terminals is greater than a maximum width of the (1-1)-th connecting terminals.
The determination and selection of parameters including dimensions (length, width, thickness, diameter, etc.), via layout/configuration, a pitch/spacing, a total number and a shape thereof, a ratio of dimensions, etc., of a via/plug, pad, trace/wiring, solder ball/bump, etc., in Semiconductor Device (SD) Packaging Technology art is a subject of routine experimentation and optimization to achieve improved metal fill, bonding strength, reliability and reduced stress.
Therefore, It would have been obvious to one having ordinary skill in the art at the time the invention was made to provide the (1-2)-th substrate pads have a smaller maximum width than the (1-1)-th substrate pads, the (2-2)-th substrate pads have a smaller maximum width than the (2-1)-th substrate pads and a maximum width of the (1-2)-th connecting terminals is greater than a maximum width of the (1-1)-th connecting terminals, in order to optimize to achieve improved metal fill, bonding strength, reliability and reduced stress.
The limitations “transmit first signals, ground signals, or power signals and …transmit second signals” has not been given patentable weight because it is considered to be functional language. This type of description does not affect the structure of the final device. It is respectfully noted that other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In a claim drawn to a process of making, the intended use must result in a manipulative difference as compared to the prior art. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). Note that Applicant has burden of proof in such cases, as the above case law makes clear. Furthermore, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Also, the limitation “a second signal that are faster than the first signals” is drawn to an operation of the device. Jung et al. teach the (1-2)-th substrate, the (1-1)-th substrate pads, the (2-2)-th substrate pads, the (2-1)-th substrate pads and the (1-2)-th connecting terminals and the (1-1)-th connecting terminals comprise conductive materials and have the same structure as claimed invention; therefore, it is capable to have transmit first signals, ground signals, or power signals and a second signal that are faster than the first signals.
As for claim 3, Jung et al. disclose the semiconductor package of claim 2, wherein bottom surfaces of the (1-2)-th connecting terminals are coplanar with bottom surfaces of the (1-1)-th connecting terminals (Fig. 1).
As for claims 4-5, Jung et al. disclose the semiconductor package of claim 1, further comprising: (1-1)-th connecting pads and (1-2)-th connecting pads 214 disposed on a third (lower) surface of the interposer 200 that faces the second surface of the package substrate (fig. 1), wherein the second connecting terminals include (2-1)-th connecting terminals (some of 205) that are disposed between the (1-1)-th connecting pads and the (2-1)-th substrate pads (Fig. 1), and (2-2)-th connecting terminals (other of 205) that are disposed between the (1-2)-th connecting pads and the (2-2)-th substrate pads (Fig. 1).
Jung et al. do not disclose the (1-2)-th connecting pads have a smaller maximum width than the (1-1)-th connecting pads and a maximum width of the (2-2)-th connecting terminals is greater than a maximum width of the (2-1)-th connecting terminals.
The determination and selection of parameters including dimensions (length, width, thickness, diameter, etc.), via layout/configuration, a pitch/spacing, a total number and a shape thereof, a ratio of dimensions, etc., of a via/plug, pad, trace/wiring, solder ball/bump, etc., in Semiconductor Device (SD) Packaging Technology art is a subject of routine experimentation and optimization to achieve improved metal fill, bonding strength, reliability and reduced stress.
Therefore, It would have been obvious to one having ordinary skill in the art at the time the invention was made to include the (1-2)-th connecting pads have a smaller maximum width than the (1-1)-th connecting pads and a maximum width of the (2-2)-th connecting terminals is greater than a maximum width of the (2-1)-th connecting terminals, in order to optimize to achieve improved metal fill, bonding strength, reliability and reduced stress.
As for claim 6, Jung et al. disclose the semiconductor package of claim 1, further comprising: (2-1)-th connecting pads (some of 305) and (2-2)-th connecting pads (others of 305) disposed on a fourth (upper) surface of the interposer 200 that faces the first semiconductor chip 400/500 (fig. 1), wherein the (2-1)-th connecting pads and the (2-2)-th connecting pads have a same maximum width (fig. 1), wherein the (2-1)-th connecting pads transmit the first signals, the ground signals, or the power signals, and the (2-2)-th connecting pads transmit the second signals (fig. 1, see claim 1 rejection for the functional limitation).
As for claim 7, Jung et al. disclose the semiconductor package of claim 1, further comprising: (2-1)-th connecting pads (some of 305) and (2-2)-th connecting pads (others of 305) disposed on a fourth (upper) surface of the interposer 200 that faces the first semiconductor chip, wherein the (2-1)-th connecting pads transmit the first signals, the ground signals, or the power signals, and the (2-2)-th connecting pads transmit the second signals (Fig. 1).
Jung et al. do not disclose the (2-2)-th connecting pads have a smaller maximum width than the (2-1)-th connecting pads.
The determination and selection of parameters including dimensions (length, width, thickness, diameter, etc.), via layout/configuration, a pitch/spacing, a total number and a shape thereof, a ratio of dimensions, etc., of a via/plug, pad, trace/wiring, solder ball/bump, etc., in Semiconductor Device (SD) Packaging Technology art is a subject of routine experimentation and optimization to achieve improved metal fill, bonding strength, reliability and reduced stress.
Therefore, It would have been obvious to one having ordinary skill in the art at the time the invention was made to include the (2-2)-th connecting pads have a smaller maximum width than the (2-1)-th connecting pads, in order to optimize to achieve improved metal fill, bonding strength, reliability and reduced stress.
As for claim 8, Jung et al. disclose the semiconductor package of claim 1, further comprising: a heat dissipation structure 600 disposed on the second surface of the package substrate 100, wherein the heat dissipation structure 600 covers the first semiconductor chip 400/500 (Fig. 1).
As for claim 15, Jung et al. disclose the semiconductor package of claim 14, wherein the second connecting terminals 205 include (2-1)-th connecting terminals (some of 205) disposed on the (1-1)-th connecting pads and (2-2)-th connecting terminals (other of 205) disposed on the (1-2)-th connecting pads (Fig. 1-2B).
Jung et al. do not disclose a maximum width of the (2-2)-th connecting terminals is greater than a maximum width of the (2-1)-th connecting terminals.
The determination and selection of parameters including dimensions (length, width, thickness, diameter, etc.), via layout/configuration, a pitch/spacing, a total number and a shape thereof, a ratio of dimensions, etc., of a via/plug, pad, trace/wiring, solder ball/bump, connecting terminals etc., in Semiconductor Device (SD) Packaging Technology art is a subject of routine experimentation and optimization to achieve improved metal fill, bonding strength, reliability and reduced stress.
Therefore, It would have been obvious to one having ordinary skill in the art at the time the invention was made to include a maximum width of the (2-2)-th connecting terminals is greater than a maximum width of the (2-1)-th connecting terminals, in order to optimize to achieve improved metal fill, bonding strength, reliability and reduced stress.
As for claim 17, Jung et al. disclose the semiconductor package of claim 14, further comprising: (1-1)-th substrate pads and (1-2)-th substrate pads disposed on the first surface of the package substrate, wherein the (1-1)-th substrate pads and the (1-2)-th substrate pads have the first connecting terminals disposed thereon, wherein a maximum width of the (1-2)-th substrate pads is less than a maximum width of the (1-1)-th substrate pads, the (1-1)-th substrate pads transmit the first signals, the ground signals, or the power signals, and the (1-2)-th substrate pads transmit the second signals.
(1-1)-th substrate pads (some of terminal pads, [0025]) and (1-2)-th substrate pads (others of terminal pads, [0025]) disposed on the first surface of the package substrate; wherein the (1-1)-th substrate pads and the (1-2)-th substrate pads have first connecting terminals 105 disposed thereon (Fig. 1);
Jung et al. do not disclose a maximum width of the (1-2)-th substrate pads is less than maximum width of the (1-1)-th substrate pads.
The determination and selection of parameters including dimensions (length, width, thickness, diameter, etc.), via layout/configuration, a pitch/spacing, a total number and a shape thereof, a ratio of dimensions, etc., of a via/plug, pad, trace/wiring, solder ball/bump, etc., in Semiconductor Device (SD) Packaging Technology art is a subject of routine experimentation and optimization to achieve improved metal fill, bonding strength, reliability and reduced stress.
Therefore, It would have been obvious to one having ordinary skill in the art at the time the invention was made to provide a maximum width of the (1-2)-th substrate pads is less than maximum width of the (1-1)-th substrate pads, in order to optimize to achieve improved metal fill, bonding strength, reliability and reduced stress.
The limitation “transmit first signals, ground signals, or power signals and …transmit second signals” has not been given patentable weight because it is considered to be functional language. This type of description does not affect the structure of the final device. It is respectfully noted that other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In a claim drawn to a process of making, the intended use must result in a manipulative difference as compared to the prior art. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). Note that Applicant has burden of proof in such cases, as the above case law makes clear. Furthermore, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
As for claim 20, Jung et al. disclose in Figs. 1-2B and the related text a semiconductor package, comprising:
a package substrate 100 that includes first (lower) and second (upper) surfaces that are opposite to each other;
(1-1)-th substrate pads (some of terminal pads, [0025]) and (1-2)-th substrate pads (others of terminal pads, [0025]) disposed on the first surface of the package substrate;
first connecting terminals 105 disposed on the (1-1)-th substrate pads and the (1-2)-th substrate pads (Fig. 1);
(2-1)-th substrate pads (some of substrate pads, [0031]) and (2-2)-th substrate pads (others of substrate pads, [0031]) disposed on the second surface of the package substrate (Fig. 1);
an interposer 200 disposed on the second surface of the package substrate 100 (Fig. 1), wherein the interposer 200 includes a third (lower) surface that faces the second surface and a fourth (upper) surface that is opposite to the third surface (fig. 1);
(1-1)-th connecting pads (some of 214a) and (1-2)-th connecting pads (others of 214a) disposed on the third surface of the interposer (fig. 1-2B), wherein the (1-2)-th connecting pads have a smaller maximum width than the (1-1)-th connecting pads (fig. 2A-2B);
second connecting terminals 205 disposed between the (1-1)-th connecting pads, and between the (2-2)-th substrate pads and the (2-1)-th substrate pads and the (1-1)-th connecting pads and between the (2-2)-th substrate pads and the (1-2)-th connecting pads (fig. 1-2B);
(2-1)-th connecting pads (some of 305) and (2-2)-th connecting pads (others of 305) disposed on the fourth surface of the interposer (fig. 1), wherein the the (2-1)-th connecting pads and the (2-2)-th connecting pads have a same maximum width (Fig. 1);
a semiconductor chip 400/500 disposed on the fourth surface of the interposer (fig. 1);
first chip pads (upper portion of some of 405/505) and second chip pads (upper portion of others of 405/505) disposed on a fifth (lower) surface of the semiconductor chip 400/500 that faces the fourth surface of the interposer 200, wherein the first chip pads and the second chip pads have a same width (Fig. 1); and
third connecting terminals (lower portion of 405/505) disposed between the (2-1)-th connecting pads and the first chip pads and between the (2-2)-th connecting pads and the second chip pads (Fig. 1).
Jung et al. do not disclose the (1-2)-th substrate pads have a smaller maximum width than the (1-1)-th substrate pads and wherein the (2-2)-th substrate pads have a smaller maximum width than the (2-1)-th substrate pads.
The determination and selection of parameters including dimensions (length, width, thickness, diameter, etc.), via layout/configuration, a pitch/spacing, a total number and a shape thereof, a ratio of dimensions, etc., of a via/plug, pad, trace/wiring, solder ball/bump, etc., in Semiconductor Device (SD) Packaging Technology art is a subject of routine experimentation and optimization to achieve improved metal fill, bonding strength, reliability and reduced stress.
Therefore, It would have been obvious to one having ordinary skill in the art at the time the invention was made to provide the (1-2)-th substrate pads have a smaller maximum width than the (1-1)-th substrate pads and wherein the (2-2)-th substrate pads have a smaller maximum width than the (2-1)-th substrate pads, in order to optimize to achieve improved metal fill, bonding strength, reliability and reduced stress.
The limitation “the (1-1)-th substrate pads, the (2-1)-th substrate pads, the (1-1)-th connecting pads, the (2-1)-th connecting pads, and the first chip pads transmit first signals, ground signals, or power signals, and the (1-2)-th substrate pads, the (2-2)-th substrate pads, the (1-2)-th connecting pads, the (2-2)-th connecting pads, and the second chip pads transmit second signals that have a different speed from the first signals” has not been given patentable weight because it is considered to be functional language. This type of description does not affect the structure of the final device. It is respectfully noted that other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In a claim drawn to a process of making, the intended use must result in a manipulative difference as compared to the prior art. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). Note that Applicant has burden of proof in such cases, as the above case law makes clear. Furthermore, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Also, the limitation “transmit second signals that have a different speed from the first signals” is drawn to an operation of the device. Jung et al. teach the (1-1)-th substrate pads, the (2-1)-th substrate pads, the (1-1)-th connecting pads, the (2-1)-th connecting pads, and the first chip pads, the (1-2)-th substrate pads, the (2-2)-th substrate pads, the (1-2)-th connecting pads, the (2-2)-th connecting pads, and the second chip pads comprise conductive materials and having the same structure as claim invention, therefore it is capable to have transmit second signals that have a different speed from the first signals).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. in view Chen et al. (US 2020/0006181).
As for claim 18, Jung et al. disclose the semiconductor package of claim 14, further comprising: a heat dissipation structure 600 disposed on the second surface of the package substrate (fig. 1), wherein the heat dissipation structure 600 covers the semiconductor chip 400/500 (Fig. 1).
Jung et al. do not disclose a first underfill material layer disposed on the second surface of the package substrate, wherein the first underfill material layer surrounds the second connecting terminals; a second underfill material layer disposed on the fourth surface of the interposer, wherein the second underfill material layer surrounds the third connecting terminals.
Chen et al. teach in Fig. 8 and the related text a first underfill material layer 802 disposed on the second surface of the package substrate 702, wherein the first underfill material layer 802 surrounds the second connecting terminals 402; a second underfill material layer 202 disposed on the fourth surface of the interposer 602, wherein the second underfill material layer 202 surrounds the third connecting terminals 104.
Jung et al. and Chen et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jung et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Jung et al. to include the limitations as taught by Chen et al. in order to provide mechanical support and protecting conductive elements.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached Monday-Thursday (9am-4pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TRANG Q TRAN/Primary Examiner, Art Unit 2811