DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claims 1 and 3 in the Applicant’s response dated 9 March 2026. The claim amendments have been addressed below.
The Examiner acknowledges the addition of new claims 21-26 in the Applicant’s response dated 9 March 2026. The new claims have been addressed below.
The Examiner acknowledges the cancellation of claims 14-20 in the Applicant’s response dated 9 March 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 13 and 21-26 are rejected under 35 U.S.C. 103 as being unpatentable over Yefei Han et al. (US 2021/0296332 A1; hereinafter “Han”) in view of Taisoo Lim et al. (US 2021/0066346 A1; hereinafter “Lim”).
Regarding Claim 1, Han teaches a memory device, comprising:
an alternating stack of insulating layers (32, Fig. 5, para [0029] describes interlayer insulating films 32) and electrically conductive layers (WL, Fig. 5, para [0047] describes word lines comprised of a conductive material);
a memory opening vertically extending through the alternating stack (MO, annotated Fig. 4, wherein a memory opening MO is comprised of memory opening fill components) and having a lateral undulation in a vertical cross-sectional profile such that the memory opening laterally protrudes outward at levels of the electrically conductive layers (470D, Fig. 5, para [0092] describes a recess portion 470D representing a lateral undulation wherein there is an opening of the recess portion from which memory fill components are located); and
a memory opening fill structure (MOFS, annotated Fig. 4, wherein memory fill components comprise components located inside memory opening MO) located in the memory opening and comprising a vertical stack of blocking dielectric material portions located at the levels of the electrically conductive layer (450 and 460, Fig. 4 and Fig. 5, para [0092] describes a block insulating film comprised of a first portion 450 and a second portion 460 which is located at levels of the electrically conductive layers WL and part of a memory opening fill structure MOFS) a vertical stack of discrete memory elements located at the levels of the electrically conductive layers (WL, Fig. 1 depicts wherein a vertical stack of memory elements are present at electrically conductive layers WL) and comprising a respective contoured charge storage material portion (FG, Fig. 4 and Fig. 5, para [0031] describes a floating gate electrode FG which charges the storage state of electrons located at levels of the electrically conductive layers) having a straight outer cylindrical sidewall (SO, annotated Fig. 4, depicts an outer cylindrical sidewall SO of charge storage material FG) and a contoured inner sidewall having an inner cylindrical sidewall segment (CI, annotated Fig. 4, depicts a contoured inner sidewall CI of charge storage material FG), an upper annular convex sidewall segment (UA, annotated Fig. 4 and annotated Fig. 5, depicts an upper annular convex sidewall segment UA of charge storage material FG), and a lower annular convex sidewall segment (LA, annotated Fig. 5, depicts a lower annular convex sidewall segment LA of charge storage material FG), a tunneling dielectric layer overlying the contoured inner sidewalls of the contoured charge storage material portion (63, Fig. 4 and Fig. 5, para [0065] describes a tunneling insulating film 63 which can be seen overlying the contoured inner sidewalls CI in annotated Fig. 4), and a vertical semiconductor channel (61, Fig. 4 and Fig. 5, para [0093] describes a channel 61 which can be seen as being a vertical channel).
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Han fails to explicitly disclose wherein the tunneling dielectric layer comprises a contoured inner sidewall that contacts a contoured outer sidewall of the vertical semiconductor channel; and first segments of the contoured inner sidewall of the tunneling dielectric layer which are located at the levels of the electrically conductive layers are laterally recessed inward toward a center axis of the memory opening relative to second segments of the contoured inner sidewall of the tunneling dielectric layer which are located at levels of the insulating layers.
However, Lim teaches a similar memory device wherein the tunneling dielectric layer comprises a contoured inner sidewall that contacts a contoured outer sidewall of the vertical semiconductor channel (142 and 140, Fig. 5B, para [0054] describes a tunneling insulating layer 142 comprising a contoured inner sidewall as a result of charge storage layers 143b wherein a contoured inner sidewall of the tunneling insulating layer 142 contacts a similarly contoured outer sidewall of a vertical channel layer 140); and
first segments of the contoured inner sidewall of the tunneling dielectric layer which are located at the levels of the electrically conductive layers (F1, annotated Fig. 5B depicts first segments F1 of the contoured inner sidewall of the tunneling dielectric layer 142 which are located at levels of electrically conductive layers 130) are laterally recessed inward toward a center axis of the memory opening relative to second segments of the contoured inner sidewall of the tunneling dielectric layer which are located at levels of the insulating layers (S1, annotated Fig. 5B depicts second segments S1 of the contoured inner sidewall of the tunneling dielectric layer 142 which are located at levels of insulating layers 120 wherein Fig. 5B depicts the first segments F1 are laterally recessed inward toward a center axis of a memory opening 150 relative to second segments S1).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Han with Lim to further disclose a memory device wherein a tunneling dielectric layer has a contoured inner sidewall with a first segment at a level of electrically conductive layers that is laterally recessed relative to a second segment located at levels of insulating layers in order to provide the well-known advantage providing a tunneling dielectric layer that may be conformally deposited between a charge storage material layer and a channel layer allowing the tunnel dielectric layers to effectively tunnel a charge to the charge storage layers further increasing device reliability (Lim, para [0036]).
Regarding Claim 2, the combination of Han and Lim teaches the memory device of Claim 1, wherein the contoured charge storage material portion comprises an outer portion having a first height (Han, FH, annotated Fig. 5 II, wherein an outer portion has a first height FH) and an inner portion having a second height greater than the first height (Han, SH, annotated Fig. 5 II, wherein an inner portion has a second height SH that is greater than the first height FH as shown in annotated Fig. 5 II below).
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Regarding Claim 3, the combination of Han and Lim teaches the memory device of Claim 1, wherein:
the respective contoured charge storage material portions comprise a material selected from ruthenium, tungsten, silicon nitride, or silicon (Han, FG, Fig. 4 and Fig. 5, para [0050] describes wherein the contoured charge storage material FG is made of, for example, polysilicon); and
the blocking dielectric material portions comprise silicon oxide (Han, 450 and 460, Fig. 5, para [0058] wherein a first blocking insulating film 45, of a comparative example of the first blocking film portion 450 of Fig. 5 and para [0092], may be formed of a stacked film including silicon oxide).
Regarding Claim 4, the combination of Han and Lim teaches the memory device of Claim 1, wherein:
the blocking dielectric material portions (Han, 450 and 460) are discrete blocking dielectric material portions that are vertically spaced apart from each other and interlaced with a vertical stack of dielectric cover material portions along a vertical direction (Han, 470, Fig. 5, para [0092] describes a third block insulating film 470 which is a dielectric material which covers the discrete blocking material portions 450 and 460 and vertically separates them from adjacent discrete blocking material portions as shown in Fig. 5); and
the dielectric cover material portions comprise a material selected from silicon oxynitride, carbon-doped silicon oxynitride, or silicon oxide (Han, para [0067] describes wherein a dielectric cover material portion 47, of a comparative example of the dielectric cover material portion 470 of Fig. 5 and para [0092], is made of, for example, silicon oxide).
Regarding Claim 5, the combination of Han and Lim teaches the memory device of Claim 4, wherein each of the dielectric cover material portions (Han, 470) contacts a cylindrical sidewall (Han, ILCS, annotated Fig. 5 III, wherein dielectric cover material portion contacts a cylindrical sidewall ILCS of insulating layer 32), an annular top surface segment (Han, ILATS, annotated Fig. 5 III, wherein dielectric cover material portion contacts an annular top surface ILATS of insulating layer 32), and an annular bottom surface segment (Han, ILABS, annotated Fig. 5 III, wherein dielectric cover material portion contacts an annular bottom surface segment of insulating layer 32) of a respective insulating layer of the insulating layers of the alternating stack (32).
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Regarding Claim 6, the combination of Han and Lim teaches the memory device of Claim 4, wherein each of the dielectric cover material portions comprises an upper annular concave surface segment (Han, CMUA, annotated Fig. 4 II, wherein dielectric cover material 470 comprises an upper annular concave surface segment CMUA) and a lower annular concave surface segment (Han, CMLA, annotated Fig. 4 II, wherein dielectric cover material 470 comprises a lower annular concave surface segment CMLA).
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Regarding Claim 7, the combination of Han and Lim teaches the memory device of Claim 4, wherein each of the blocking dielectric material portions (Han, 450 and 460) comprise a respective inner cylindrical sidewall (Han, BICS, annotated Fig. 5 IV depicts an inner cylindrical sidewall BICS of the blocking dielectric material 450) that contacts a straight outer cylindrical sidewall of a respective contoured charge storage material portion (Han, annotated Fig. 5 IV, wherein BICS can be seen in contact with the straight outer cylindrical sidewall SO of the contoured charge storage material portion FG), a respective outer cylindrical sidewall (Han, BOCS, annotated Fig. 5 IV depicts an outer cylindrical sidewall BOCS of the blocking dielectric material 450), a respective upper annular top surface (Han, BUATS, annotated Fig. 5 IV depicts an upper annular top surface of the blocking dielectric material 450), and a respective lower annular top surface (Han, BLATS, annotated Fig. 5 IV depicts a lower annular top surface of the blocking dielectric material 450).
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Regarding Claim 8, the combination of Han and Lim teaches the memory device of Claim 4, wherein each of the blocking dielectric material portions comprises nitrogen atoms (Han, 450 and 460, Fig. 5, para [0058] and para [0092] describes wherein a second portion of a blocking insulating film 45, of a comparative example of the first blocking film portion 450 of Fig. 5 and para [0092], may be comprised of a stacked film of silicon oxide and silicon nitride) at a variable atomic concentration that decreases with a lateral distance from a cylindrical interface with a respective one of the contoured charge storage material portions (Han, 450 and 460, Fig. 5, para [0062] describes wherein a second portion of a blocking insulating film 46, of a comparative example of the second blocking film portion 460 of Fig. 5 and para [0092], which is at a further lateral distance from a cylindrical interface with a respective one of the contoured charge storage material portions, may be comprised of a material that does not contain nitrogen such as hafnium oxide thereby having a decreased nitrogen concentration).
Regarding Claim 13, the combination of Han and Lim teaches the memory device of Claim 1, wherein each of the electrically conductive layers is spaced from a respective neighboring pair of insulating layers of the insulating layers of the alternating stack and from the memory opening fill structure by a respective backside blocking dielectric layer (Han, BO, Fig. 5, para [0047] describes a block film BO which can be seen separating the conductive layer WL from adjacent insulating layers 32 and from the memory opening fill structure MOFS) comprising a dielectric metal oxide material (Han, para [0047] describes wherein backside blocking dielectric layer BO is made of, for example, aluminum oxide).
Regarding Claim 21, Han teaches a memory device, comprising:
an alternating stack of insulating layers (32, Fig. 6, para [0029] describes interlayer insulating films 32) and electrically conductive layers (WL, Fig. 6, para [0047] describes word lines comprised of a conductive material);
a memory opening vertically extending through the alternating stack (MO, annotated Fig. 4, wherein a memory opening MO is comprised of memory opening fill components) and having a lateral undulation in a vertical cross-sectional profile such that the memory opening laterally protrudes outward at levels of the electrically conductive layers (47D, Fig. 6, para [0103] describes a recess portion 470D representing a lateral undulation wherein there is an opening of the recess portion from which memory fill components are located); and
a memory opening fill structure (MOFS, annotated Fig. 4, wherein memory fill components comprise components located inside memory opening MO) located in the memory opening and comprising a vertical stack of blocking dielectric material portions located at the levels of the electrically conductive layers (45, 46 and 48, Fig. 4 and Fig. 6, para [0058] describes a block insulating film comprised of a first portion 45, a second portion 46 and a fourth portion 48 wherein the block insulating film structure is located at levels of the electrically conductive layers WL and part of a memory opening fill structure MOFS), a vertical stack of discrete memory elements located at the levels of the electrically conductive layers (FG, Fig. 4 and Fig. 6, para [0031] describes a floating gate electrode FG which charges the storage state of electrons located at the levels of the electrically conductive layers WL), a tunneling dielectric layer overlying inner sidewalls of the discrete memory elements (63, annotated Fig. 4 and Fig. 6, para [0065] describes a tunneling insulating film 63 which can be seen overlying the contoured inner sidewalls CI in annotated Fig. 4), and a vertical semiconductor channel (61, para [0075] describes a vertical semiconductor channel 61).
Han fails to explicitly disclose wherein the tunneling dielectric layer comprises a contoured outer sidewall having first segments that contact the discrete memory elements at the levels of the electrically conductive layers and having second segments that contact the blocking dielectric material portions at levels of the insulating layers; and the first segments of the contoured outer sidewall of the tunneling dielectric layer are laterally recessed inward toward a center axis of the memory opening relative to the second segments of the contoured outer sidewall of the tunneling dielectric layer.
However, Lim teaches a similar memory device wherein:
the tunneling dielectric layer comprises a contoured outer sidewall having first segments that contact the discrete memory elements at the levels of the electrically conductive layers (F2, annotated Fig. 5B II, para [0054] describes a contoured outer sidewall of a tunneling dielectric layer 142 comprising first segments F2 contacting discrete memory elements 143b at the levels of electrically conductive layers 130) and having second segments that contact the blocking dielectric material portions at levels of the insulating layers (S2, annotated Fig. 5B II para [0054] describes contoured outer sidewall segments of the tunneling dielectric layer 142 comprising second segments S2 contacting a blocking dielectric layer 144 wherein upon combining with Han with Lim, the tunneling dielectric layer 142 second segments S of Lim would extend to contact the blocking dielectric portion 48 at levels of the insulating layers 32 of Han as shown in Fig. 6); and
the first segments of the contoured outer sidewall of the tunneling dielectric layer are laterally recessed inward toward a center axis of the memory opening relative to the second segments of the contoured outer sidewall of the tunneling dielectric layer (F2 and S2, annotated Fig. 5B II depicts wherein first segments F2 are laterally recessed toward a center axis of the memory opening 150 relative to the second segments S2 of the contoured outer sidewall of the tunneling dielectric layer 142).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Han with Lim to further disclose a memory device wherein a tunneling dielectric layer has a contoured outer sidewall with a first segment at a level of electrically conductive layers that is laterally recessed inward relative to a second segment located at levels of insulating layers in order to provide the well-known advantage providing a tunneling dielectric layer that may be conformally deposited between a charge storage material layer and a channel layer allowing the tunnel dielectric layers to effectively tunnel a charge to the charge storage layers further increasing device reliability (Lim, para [0036]).
Regarding Claim 22, the combination of Han and Lim teaches the memory device of Claim 21, wherein each of the discrete memory elements comprises a respective contoured charge storage material portion (Han, FG, Fig. 4 and Fig. 6, para [0031] describes a floating gate electrode FG which charges the storage state of electrons wherein the floating gate electrode FG is comprised in a discrete memory element including word lines WL) having a straight outer cylindrical sidewall (Han, SO, annotated Fig. 4, depicts an outer cylindrical sidewall SO of charge storage material FG) and a contoured inner sidewall having an inner cylindrical sidewall segment (Han, CI, annotated Fig. 4, depicts a contoured inner sidewall CI of charge storage material FG), an upper annular convex sidewall segment (Han, UA2, annotated Fig. 4 and annotated Fig.6, depicts an upper annular convex sidewall segment UA2 of charge storage material FG), and a lower annular convex sidewall segment (Han, LA2, annotated Fig. 6, depicts a lower annular convex sidewall segment LA of charge storage material FG).
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Regarding Claim 23, the combination of Han and Lim teaches the memory device of Claim 22, wherein the respective contoured charge storage material portion comprises an outer portion having a first height (Han, FH2, annotated Fig. 6 II, wherein an outer portion has a first height FH2) and an inner portion having a second height greater than the first height (Han, SH2, annotated Fig. 6 II, wherein an inner portion has a second height SH2 that is greater than the first height FH2 as shown in annotated Fig. 6 II below).
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Regarding Claim 24, the combination of Han and Lim teaches the memory device of Claim 21, wherein:
the blocking dielectric material portions (Han, 45, 46 and 48, Fig. 6) are discrete blocking dielectric material portions that are vertically spaced apart from each other and interlaced with a vertical stack of dielectric cover material portions along a vertical direction (Han, 47, Fig. 6, para [0064] describes a third block insulating film 47 which is a dielectric material interlaced with discrete blocking dielectric material portion 45, 45 and 48 wherein the dielectric cover material portion 47 covers the discrete blocking material portions 45, 46 and 48 and vertically separates them from adjacent discrete blocking material portions as shown in Fig. 6); and
the dielectric cover material portions comprise a material selected from silicon oxynitride, carbon-doped silicon oxynitride, or silicon oxide (Han, 47, Fig. 6, para [0067] describes wherein the dielectric cover material portion 47 is made of, for example, silicon oxide).
Regarding Claim 25, the combination of Han and Lim teaches the memory device of Claim 24, wherein each of the dielectric cover material portions contacts a cylindrical sidewall (Han, CS2, annotated Fig. 6 III, wherein dielectric cover material portion contacts a cylindrical sidewall CS2 of insulating layer 32), an annular top surface segment (Han, ATS2, annotated Fig. 6 III, wherein dielectric cover material portion contacts an annular top surface ATS2 of insulating layer 32), and an annular bottom surface segment (Han, ABS2, annotated Fig. 6 III, wherein dielectric cover material portion contacts an annular bottom surface segment ABS2 of insulating layer 32) of a respective insulating layer of the insulating layers of the alternating stack (Han, 32, Fig. 6).
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Regarding Claim 26, the combination of Han and Lim teaches the memory device of Claim 21, wherein each of the electrically conductive layers is spaced from a respective neighboring pair of insulating layers of the insulating layers of the alternating stack and from the memory opening fill structure by a respective backside blocking dielectric layer (BO, Fig. 6, para [0047] describes a block film BO which can be seen separating the conductive layer WL from adjacent insulating layers 32 and from the memory opening fill structure MOFS of annotated Fig. 4) comprising a dielectric metal oxide material (BO, Fig. 6, para [0047] describes wherein backside blocking dielectric layer BO is made of, for example, aluminum oxide).
Response to Arguments
Applicant’s arguments with respect to claims 1-8, 13 and 21-26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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