Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action mailed on 01/08/2026 ("01-08-26 Final OA") has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/08/2026 ("05-08-26 Submission") has been entered when the RCE was filed on 05/08/2026.
In the 05-08-26 Submission, the Applicant substantively amended independent claim 11 and its dependent claims 12-15.
Currently, amended claims 1-4, 6-15 and 17-22 are pending and are examined below.
Response to Arguments
Applicant's amendments to the independent claim 11 have overcome the 35 U.S.C. 102(a)(2) rejection of claim 11 set forth starting on page 3 under line item number 1 of the 01-08-26 Final OA.
Substantive amendments to claims 11-15 required further consideration and search, however. During the new search, a new reference Kim, infra, was considered against previously-indicated allowed claims.New grounds of rejections are provided below.
A. Prior-art rejections based on Kim
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-4, 7-15 and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2023/0127641 A1 to Kim et al. (“Kim”).
Fig. 28 of Kim has been annotated to support the rejections below:
[AltContent: textbox (UC)][AltContent: textbox (Inf)][AltContent: arrow][AltContent: arrow][AltContent: textbox (Vias)][AltContent: arrow][AltContent: arrow]
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Regarding independent claim 1, Kim teaches a structure (para [0089]- “FIG. 28 is an enlarged cross-sectional view illustrating a portion I in FIG. 27. FIG. 29 is a cross-sectional view illustrating a semiconductor strip including a molding member from which a curl portion and a dummy curl portion in FIG. 26 are removed.”), comprising:
an integrated circuit (IC) die 200, 400 (An IC die 200 has been construed to include the interposer 400 as well. Thus, an IC die encompasses chip 200 with the interposer 400.);
an interposer structure 110, 124, 126 (para [0061]) electrically connected to the IC die 200, 400;
a first bonding structure 250, 260 (para [0070] - “a connection member 250”; para [0071] - “an underfill member 260”), comprising:
a first dielectric layer 260 disposed on the IC dies 200, 400; and
a first conductive plug 250 disposed in the first dielectric layer 260;
a second bonding structure 140, 122 (para [0063] - “a first passivation layer pattern 140”; para [0061] - “wirings 122, 124, 126 and 128”) bonded to the first bonding structure 250, 260, wherein the second bonding structure 140, 122 comprises:
a second dielectric layer 140 disposed on the interposer structure 110; and
a second conductive plug 122 disposed in the second dielectric layer 140; and
a molding compound layer 130 (para [0028] - “…the molding member 300 may include a sealing portion covering the semiconductor chips 200, a curl portion and a dummy curl portion, gate runner portions may be provided between the sealing portion and the curl portion, and dummy runner portions may be provided between the sealing portion and the dummy portion.”) disposed on the second bonding structure 140, 122, wherein the molding compound layer 130 comprises a mold region 130a and a mold cavity UC, and wherein the mold cavity extends below an interface Inf between the IC die 200, 400 and the first bonding structure 250, 260.
Regarding claim 2, Kim teaches the molding compound layer 300 that surrounds the IC die 200, 400 and the first bonding structure 250, 260.
Regarding claim 3, Kim teaches the mold region 300a that is disposed directly on sidewalls of the IC die 200, 400 and the first dielectric layer 260.
Regarding claim 4, Kim teaches the mold region 300a and the mold cavity UC that are disposed on a portion (aligned with connection member 450) of the second bonding structure 140, 122 non-overlapping with the first bonding structure 250, 260.
Regarding claim 7, Kim teaches the mold cavity UC that comprises a U-shaped cross-sectional profile.
Regarding claim 8, Kim teaches the mold cavity UC that comprises first and second mold cavities disposed in the mold region 300a (see Fig. 26).
Regarding claim 9, Kim teaches an interface between the mold region 300a and the second bonding structure 140, 122 that is substantially coplanar with an interface between the first structure 250, 260 and second bonding structure 140, 122.
Regarding claim 10, Kim teaches a top surface of the mold region 300a that is substantially coplanar with a back surface of the IC die 200, 400.
Regarding independent claim 11, Kim teaches an integrated circuit (IC) die package (para [0089]- “FIG. 28 is an enlarged cross-sectional view illustrating a portion I in FIG. 27. FIG. 29 is a cross-sectional view illustrating a semiconductor strip including a molding member from which a curl portion and a dummy curl portion in FIG. 26 are removed.”), comprising:
a routing layer 120 comprising conductive lines 122, 124, 126, 128 (para [0061] - “wirings 122, 124, 126 and 128”) and vias Vias;
first IC dies 200, 400 (Fig. 9 shows more than one semiconductor chip 200. para [0059] - “For example, 50 to 800 semiconductor chips 200 may be arranged on the substrate 100 in a matrix form.” An IC die 200 has been construed to include the interposer 400 as well. Thus, a first IC die encompasses chip 200 with the interposer 400, and a second IC dies encompasses another chip 200 with the interposer 400.) and second IC dies 200, 400 disposed on the routing layer 120;
first bonding structure 450 (para [0094] - “conductive connection members 450”) and second bonding structure 450 disposed on the first die 200, 400 and second IC die 200, 400, respectively;
a third bonding structure 250 (para [0068] - “a connection member 250”) bonded to the first and second bonding structures 450, 450 and disposed on the routing layer 120; and
an encapsulation layer 300 (para [0028] - “…the molding member 300 may include a sealing portion covering the semiconductor chips 200, a curl portion and a dummy curl portion, gate runner portions may be provided between the sealing portion and the curl portion, and dummy runner portions may be provided between the sealing portion and the dummy portion.”) disposed surrounding the first die 200, 400 and second IC die 200, 400, wherein the encapsulation layer 300 comprises a mold region 300a (para [0042] - “a sealing portion 300a”) and an unfilled cavity UC, and wherein the unfilled cavity UC extends below an interface Inf between the first IC die 200, 400 and the first bonding structure 450.
Regarding claim 12, Kim teaches the unfilled cavity UC that is disposed between the first die 200, 400 and second die 200, 400.
Regarding claim 13, Kim teaches the unfilled cavity UC that is disposed between the first bonding structure 450 and second bonding structure 250.
Regarding claim 14, Kim teaches the unfilled cavity UC that is disposed on a portion of the third bonding structure 130 (para [0064] - “adhesion reducing pad 130”) non-overlapping with the first bonding structure 450 and second bonding structure 250.
Regarding claim 15, Kim teaches a surface portion of the third bonding structure 130 non-overlapping with the first bonding structure 450 and second bonding structure 250 that is exposed (on the side S2) in the unfilled cavity UC.
Regarding claim 22, Kim teaches the mold region 300a that is disposed between the mold cavity UC and the IC die 200, 400.
B. Prior-art rejections based on Pietambaram
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-4, 7-11, 14, 15 and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pietambaram (previously-cited Pub. No. US 2020/0006232 A1 to Pietambaram et al. in the 10-01-25 OA).
Fig. 1 of Pietambaram has been annotated to support the rejection below:
[AltContent: textbox (MR)]
[AltContent: textbox (MC1)][AltContent: arrow][AltContent: arrow][AltContent: textbox (MC2)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow]
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Regarding independent claim 1, Pietambaram teaches a structure (see Fig. 1 as annotated above), comprising:
an integrated circuit (IC) die 150A or 150B (para [0038] - “a plurality of second dies 150 may be mounted over the first die 140…two dies 150 are illustrated in FIG. 1, which shows a die 150A and another die 150B.);
an interposer structure 140, 145 (para [0037] - “a first die 140”) electrically connected to the IC die 150;
a first bonding structure 154, 152 (para [0038] - “first level interconnect 152…”) an underfill material 154”), comprising:
a first dielectric layer 154 disposed on the IC die 150; and
a first conductive plug 152 disposed in the first dielectric layer 154;
a second bonding structure 145, 147 (para [0038] - “solder 147 through a die backside film (DBF) 145”) bonded to the first bonding structure 154, 152, wherein the second bonding structure 145, 147 comprises:
a second dielectric layer 145 (The DBF 145 is more likely than not at least partially made of dielectric material. Otherwise, the solder 147 would cause a short at the interface between the DBF 145 and the solder 147.) disposed on the interposer structure 140, 145; and
a second conductive plug 147 disposed in the second dielectric layer 145; and
a molding compound layer 160 (para [0037] - “encapsulation layer 160”; para [0037] - “In an embodiment, the CTE of the glass core 130 may be substantially similar to the CTE of an encapsulation layer 160 that surrounds the first die 140.”) disposed on the second bonding structure 145, 147, wherein the molding compound layer 160 comprises a mold region MR and a mold cavity MC1 and/or MC2, and the mold cavity MC1 and/or MC2 extends below an interface between the IC die 150A or 150B and the first bonding structure 154, 152.
Regarding claim 2, Pietambaram teaches the molding compound layer 160 that surrounds the IC die 150A or 150B and the first bonding structure 154, 152.
Regarding claim 3, Pietambaram teaches the mold region MR that is disposed directly on sidewalls of the IC die 150A or 150B and the first dielectric layer 154.
Regarding claim 4, Pietambaram teaches the mold region MR and the mold cavity MC1 and/or MC2 that are disposed on a portion of the second bonding structure 145, 147 non-overlapping with the first bonding structure 154, 152.
Regarding claim 7, Pietambaram teaches the mold cavity MC1 and/or MC2 that comprises a U-shaped cross-sectional profile.
Regarding claim 8, Pietambaram teaches the mold cavity MC1, MC2 that comprises first and second mold cavities MC1, MC2 disposed in the mold region MR.
Regarding claim 9, Pietambaram teaches an interface (at 160/130) between the mold region MR and the second bonding structure 145, 147 is substantially coplanar with an interface (at 145/130) between the first bonding structure 154, 152 and second bonding structures 145, 147.
Regarding claim 10, Pietambaram teaches a top surface of the mold region MR that is substantially coplanar with a back surface of the IC die 150A or 150B.
Regarding independent claim 11, Pietambaram teaches an integrated circuit (IC) die package (see Fig. 1 as annotated above), comprising:
a routing layer 120 (para [0040] - “a build-up layer 120”) comprising conductive lines 125 and vias 124 (para [0040] - “a plurality of conductive traces 125 and vias 124”);
first and second IC dies 150A, 150B (para [0038] - “a plurality of second dies 150 may be mounted over the first die 140…two dies 150 are illustrated in FIG. 1, which shows a die 150A and another die 150B.) disposed on the routing layer 120;
a first bonding structure 154, 152 and second bonding structure 145, 147 disposed on the first and second IC dies 150A, 150B, respectively;
a third bonding structure 130, 132 (para [0037] - “conductive vias 132 may be formed through the glass core 130.”) (indirectly) bonded to the first bonding structure 154, 152 and the second bonding structure 145, 147 and disposed on the routing layer 120; and
an encapsulation layer 160 (para [0037] - “encapsulation layer 160”; para [0037] - “In an embodiment, the CTE of the glass core 130 may be substantially similar to the CTE of an encapsulation layer 160 that surrounds the first die 140.”) disposed surrounding the first and second IC dies 150A, 150B, wherein the encapsulation layer 160 comprises a mold region MR and an unfilled cavity MC1 or MC2, and wherein the unfilled cavity MC1 or MC2 extends below an interface between the first IC die 150A or 150B and the first bonding structure 154, 152.
Regarding claim 14, Pietambaram teaches unfilled cavity MC1 or MC2 that is disposed on a portion of the third bonding structure 130, 132 non-overlapping with the first bonding structure 154, 152 and the second bonding structure 145, 147.
Regarding claim 15, Pietambaram teaches a surface portion of the third bonding structure 130, 132 non-overlapping with the first bonding structure 154, 152 and the second bonding structure 145, 147 that is exposed in the unfilled cavity MC1 or MC2.
Regarding claim 22, Pietambaram teaches the mold region 160 that is displayed between the mold cavity MC1 or MC2 and the IC die 150A or 150.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 6 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 6.
Independent claim 17 and its dependent claims 18-20 are allowed for the same reasons as stated on page 11 under line item number 4 of the 10-01-25 OA.
Claim 21 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 21.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
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/MICHAEL JUNG/Primary Examiner, Art Unit 2817 12 May 2026
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