Prosecution Insights
Last updated: April 19, 2026
Application No. 18/348,934

MOLDING COMPOUND LAYERS IN SEMICONDUCTOR PACKAGES

Final Rejection §102
Filed
Jul 07, 2023
Examiner
JUNG, MICHAEL YOO LIM
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Apple Inc.
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
2y 5m
To Grant
93%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
1019 granted / 1241 resolved
+14.1% vs TC avg
Moderate +11% lift
Without
With
+11.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
41 currently pending
Career history
1282
Total Applications
across all art units

Statute-Specific Performance

§101
2.1%
-37.9% vs TC avg
§103
29.0%
-11.0% vs TC avg
§102
35.0%
-5.0% vs TC avg
§112
27.6%
-12.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1241 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION In response to an Office action mailed on 10/01/2025 ("10-01-25 OA") and a telephonic interview held on 12/17/2025 (see Applicant-initiated interview summary mailed on 12/19/2025 for details), the Applicant (i) amended independent claim 1 to include the limitations of the previously-indicated allowable claim 5 and then canceled claim 5, (ii) amended claims 11-15, (iii) canceled claim 16 and (iv) added new claims 21 and 22 on 12/23/2025 ("12-23-25 Response"). Applicant also amended the title in the 12-23-25 Response. Currently, claims 1-4, 6-15 and 17-22 are pending. Response to Arguments Applicant's amendments to the title have overcome the objection to the Specification set forth on page 2 under line item number 1 of the 10-01-25 OA. Applicant's amendments to the independent claims 1 and 11 have overcome the 35 U.S.C. 102(a)(1) rejection of claims 1-4, 6-11, 14 and 15 as being anticipated by Pietambaram set forth starting on page 3 under line item number 2 of the 10-01-25 OA. Applicant's amendments to the independent claims 11 have overcome the 35 U.S.C. 102(a)(1) rejection of claims 11-13 and 16 as being anticipated by Wang set forth starting on page 9 under line item number 3 of the 10-01-25 OA. Substantive amendments to the independent claim 11 required further consideration and search. New grounds of rejections are provided below. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim 11 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pub. No. US 2025/0015062 A1 to Kang ("Kang"). Fig. 13 of Kang has been annotated to support the rejection below: [AltContent: textbox (BS1)][AltContent: arrow][AltContent: textbox (BS2)][AltContent: arrow][AltContent: rect][AltContent: rect][AltContent: arrow][AltContent: textbox (MC1)][AltContent: arrow][AltContent: textbox (MC2)][AltContent: arrow][AltContent: arrow][AltContent: textbox (MR)] PNG media_image1.png 412 644 media_image1.png Greyscale Regarding independent claim 11, Kang teaches an integrated circuit (IC) die package (see Fig. 13 as annotated above), comprising: a routing layer 100 (para [0029] - “The first redistribution substrate 100 may include one first substrate wiring layer or a plurality of first substrate wiring layers that are stacked on each other. Each of the first substrate wiring layers may include a first substrate dielectric pattern 110 and a first substrate wiring pattern 120 in the first substrate dielectric pattern 110.”) comprising conductive lines and vias (para [0032] - “[0032] The first substrate wiring pattern 120 may have a damascene structure. For example, the first substrate wiring pattern 120 may have a via that protrudes onto a top surface of first substrate wiring pattern 120. The via may be a component that vertically connects to each other the first substrate wiring patterns 120 of two neighboring first substrate wiring layers. For example, the via may extend from the top surface of the first substrate wiring pattern 120, and may penetrate the first substrate dielectric pattern 110 to be coupled to a bottom surface of the first substrate wiring pattern 120 in another first substrate wiring layer that overlies the via.”); first and second IC dies 320, 330 (para [0039]- “a first semiconductor chip 320 and a second semiconductor chip 330”) disposed on the routing layer 100; first bonding structure BS1 (a section of UP, CP that is directly under die 320) and second bonding structure BS2 (a section of UP, CP that is directly under die 330) disposed on the first and second IC dies 320, 330, respectively; a third bonding structure LP (para [0040] - “a lower buildup portion LP”) bonded to the first bonding structure BS1 and second bonding structures BS2 and disposed on the routing layer 100; and an encapsulation layer 400 (para [0054] - “A molding layer 400”) disposed surrounding the first and second IC dies 320, 330, wherein the encapsulation layer 400 comprises a mold region MR and a mold cavity MC1 and/or MC2 (an opening in the molding layer 400 that is occupied by a through electrode 450) and wherein the mold cavity MC1 and/or MC2 extends below an interface between the first IC die 320 and the first bonding structure BS1. Allowable Subject Matter The following is a statement of reasons for the indication of allowable subject matter: Independent claim 1 is allowed, because the independent claim 1 has been amended to include the limitations of the previously-indicated allowable claim 5 as stated on page 11 under line item number 4 of the 10-01-25 OA. Claims 2-4, 6-10, 21 and 22 are allowed, because they depend from the allowed independent claim 1. Claim 12 is objected to, but would be allowable if (i) its base claim 11 is amended to include all of the limitations of claim 12 or (ii) claim 12 is rewritten in independent form to include all of the limitations of its base claim 11. Claim 13 is objected to, but would be allowable if (i) its base claim 11 is amended to include all of the limitations of claim 13 or (ii) claim 13 is rewritten in independent form to include all of the limitations of its base claim 11. Claim 14 is objected to, but would be allowable if (i) its base claim 11 is amended to include all of the limitations of claim 14 or (ii) claim 14 is rewritten in independent form to include all of the limitations of its base claim 11. Claim 15 is objected to, but would be allowable if (i) its base claim 11 is amended to include all of the limitations of claim 15 or (ii) claim 15 is rewritten in independent form to include all of the limitations of its base claim 11. Independent claim 17 and its dependent claims 18-20 are allowed for the same reasons as stated on page 11 under line item number 4 of the 10-01-25 OA. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8 A.M. to 7 P.M. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano, can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL JUNG/Primary Examiner, Art Unit 2817 06 January 2026
Read full office action

Prosecution Timeline

Jul 07, 2023
Application Filed
Sep 27, 2025
Non-Final Rejection — §102
Dec 17, 2025
Applicant Interview (Telephonic)
Dec 17, 2025
Examiner Interview Summary
Dec 23, 2025
Response Filed
Jan 06, 2026
Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603132
METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS EACH WITH A FILLED TRENCH WITHIN A STADIUM STRUCTURE OF AT LEAST ONE BLOCK
2y 5m to grant Granted Apr 14, 2026
Patent 12598998
INTERPOSER AND FABRICATION THEREOF
2y 5m to grant Granted Apr 07, 2026
Patent 12593691
SEMICONDUCTOR DEVICE WITH TWO-PHASE COOLING STRUCTURE INCLUDING ULTRASONIC TRANSDUCER
2y 5m to grant Granted Mar 31, 2026
Patent 12588524
STACKED VIA MODULATOR IN HIGH SPEED INTERCONNECT
2y 5m to grant Granted Mar 24, 2026
Patent 12588528
PACKAGE BUMPS OF A PACKAGE SUBSTRATE HAVING DIAGONAL PACKAGE BUMPS
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
93%
With Interview (+11.2%)
2y 5m
Median Time to Grant
Moderate
PTA Risk
Based on 1241 resolved cases by this examiner. Grant probability derived from career allow rate.

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